Non-volatile memory with memory array between circuits

ABSTRACT

An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die comprises a three dimensional non-volatile memory structure and a first plurality of sense amplifiers. The first plurality of sense amplifiers are connected to the memory structure and are positioned on a substrate of the memory die between the memory structure and the substrate such that the memory structure is directly above the first plurality of sense amplifiers. The control die comprises a second plurality of sense amplifiers that are connected to the memory structure. The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured to be used to concurrently perform memory operations.

BACKGROUND

Semiconductor memory is widely used in various electronic devices suchas cellular telephones, digital cameras, personal digital assistants,medical electronics, mobile computing devices, servers, solid statedrives, non-mobile computing devices and other devices. Semiconductormemory may comprise non-volatile memory or volatile memory. Non-volatilememory allows information to be stored and retained even when thenon-volatile memory is not connected to a source of power (e.g., abattery). One example of non-volatile memory is flash memory (e.g.,NAND-type and NOR-type flash memory).

Users of memory systems that include non-volatile memory can write datato the non-volatile memory and later read that data back. For example, adigital camera may take a photograph and store the photograph innon-volatile memory. Later, a user of the digital camera may view thephotograph by having the digital camera read the photograph from thenon-volatile memory. Performance of memory systems is important tousers. That is, users typically do not want to wait for the memorysystem to write to or read from the non-volatile memory. For example, auser of a digital camera with non-volatile memory does not want to waitfor a first photograph to be stored before taking additionalphotographs. Therefore, there is a desire for high performance memorysystems that utilize non-volatile memory.

BRIEF DESCRIPTION OF THE DRAWINGS

Like-numbered elements refer to common components in the differentfigures.

FIG. 1 is a block diagram depicting one embodiment of a memory system.

FIG. 2 is a block diagram of one embodiment of an integrated memoryassembly.

FIG. 3 is a block diagram of one embodiment of a read/write circuit andan ECC circuit of an integrated memory assembly.

FIG. 4 is a block diagram depicting one embodiment of a sense block.

FIG. 5 is a block diagram of a memory structure that includes fourplanes.

FIG. 6 depicts a top view of a portion of a block of memory cells.

FIG. 7 depicts a cross sectional view of a portion of a block of memorycells.

FIG. 8 is a cross sectional view of a vertical column of memory cells.

FIG. 9 is a cross sectional view of one embodiment of a portion of twoblocks of memory cells.

FIG. 10 is a schematic of a plurality of NAND strings showing multiplesub-blocks.

FIG. 11 is a cross sectional view of one embodiment of a portion of twoblocks of memory cells.

FIG. 12 is a cross sectional view of one embodiment of a portion of twoblocks of memory cells.

FIGS. 12A and 12B are tables depicting bias voltages for the top andbottom select lines.

FIG. 13 is a block diagram of one embodiment of an integrated memoryassembly.

FIG. 14 is a block diagram of one embodiment of an integrated memoryassembly.

FIG. 15 depicts one embodiment of a floor plan for a control die.

FIG. 16 depicts one embodiment of a floor plan for a memory die.

FIG. 17 depicts one embodiment of a floor plan for a control die.

FIG. 18 depicts one embodiment of a floor plan for a memory die.

FIG. 19 depicts a side view of an embodiment of an integrated memoryassembly.

FIG. 20 is a block diagram of a memory structure that includes fourplanes.

FIG. 21 is a block diagram of a memory structure that includes fourplanes.

FIG. 22 depicts a top view of a portion of a block of memory cells.

FIG. 23 depicts a top view of a portion of a block of memory cells.

FIG. 24 is a flow chart describing one embodiment of a process forperforming a memory operation.

FIG. 25 is a flow chart describing one embodiment of a process forperforming a write operation.

FIG. 26 depicts threshold voltage distributions.

FIG. 27 is a table describing one example of an assignment of datavalues to data states.

FIG. 28 is a flow chart describing one embodiment of a process forprogramming non-volatile memory.

FIG. 29 is a flow chart describing one embodiment of a process forreading non-volatile memory.

FIG. 30 is a block diagram of one embodiment of an integrated memoryassembly.

DETAILED DESCRIPTION

Performance of a memory system is increased by increasing parallelismduring memory operations (e.g., writing and reading). Some memorysystems can include control circuits (e.g., including sense amplifiers)on the same die as the memory array, for example, underneath the memoryarray. Other memory systems may include control circuits (e.g.,including sense amplifiers) on a different die than the memory array. Ineach case, the amount of parallelism (e.g., amount of data that can bewritten or read concurrently) is a function of the number of senseamplifiers. By including control circuits (e.g., including senseamplifiers) on the same die as the memory array and on a different diethan the memory array, the number of sense amplifiers can be increased.Increasing the number of sense amplifiers increases the amount ofparallelism, which results in an increase in performance of the memorysystem. Additionally, increasing the amount of parallelism can result ina more efficient use of power and additional functionality.

One embodiment of a memory system introduced herein includes anintegrated memory assembly that comprises a memory die and a control diebonded (or otherwise connected) to the memory die. The memory diecomprises a three dimensional non-volatile memory structure and a firstcontrol circuit. The three dimensional non-volatile memory structure(e.g., memory array) comprises a plurality of non-volatile memory cells.The first control circuit is positioned on a substrate of the memorydie. The non-volatile memory cells are positioned directly above (e.g.,on top of, but separated by one or more layers of nonconductivematerial, such as a dielectric) the first control circuit. The firstcontrol circuit is connected to the memory cells of the threedimensional non-volatile memory structure. The control die comprises asecond control circuit that is connected to the memory cells of thethree dimensional non-volatile memory structure. The first controlcircuit is configured to be used to perform a memory operation on afirst subset of the non-volatile memory cells while the second controlcircuit is configured to be used to concurrently perform a memoryoperation on a second subset of the non-volatile memory cells.

For example, in one embodiment the first control circuit includes afirst plurality of sense amplifiers connected to a first sub-block ofthe non-volatile memory cells and the second control circuit includes asecond plurality of sense amplifiers connected to a second sub-block ofthe non-volatile memory cells. The first plurality of sense amplifiersand the second plurality of sense amplifiers are configured to be usedto concurrently perform memory operations on the first sub-block and thesecond sub-block, where the first sub-block and the second sub-block arepart of the same block of memory cells.

FIG. 1 is a block diagram of one embodiment of a memory system 100 thatimplements the technology described herein. In one embodiment, storagesystem 100 is a solid state drive (“SSD”). Memory system 100 can also bea memory card, USB drive, embedded memory, solid state drive or othertype of storage system. The proposed technology is not limited to anyone type of memory system. Memory system 100 is connected to host 102,which can be a computer, server, electronic device (e.g., smart phone,tablet or other mobile device), appliance, or another apparatus thatuses memory and has data processing capabilities. In some embodiments,host 102 is separate from, but connected to, memory system 100. In otherembodiments, memory system 100 is embedded within host 102.

The components of memory system 100 depicted in FIG. 1 are electricalcircuits. Memory system 100 includes a memory controller 120 connectedto one or more integrated memory assemblies 130 and local high speedvolatile memory 140 (e.g., DRAM). The one or more integrated memoryassemblies 130 each comprise a plurality of non-volatile memory cells.More information about the structure of each integrated memory assembly130 is provided below. Local high speed volatile memory 140 is used bycontroller 120 to perform certain functions. For example, local highspeed volatile memory 140 stores logical to physical address translationtables (“L2P tables”).

Memory controller 120 comprises a host interface 152 that is connectedto and in communication with host 102. In one embodiment, host interface152 provides a PCIe interface. Other interfaces can also be used, suchas SCSI, SATA, etc. Host interface 152 is also connected to anetwork-on-chip (NOC) 154. A NOC is a communication subsystem on anintegrated circuit. NOC's can span synchronous and asynchronous clockdomains or use unclocked asynchronous logic. NOC technology appliesnetworking theory and methods to on-chip communications and bringsnotable improvements over conventional bus and crossbarinterconnections. NOC improves the scalability of systems on a chip(SoC) and the power efficiency of complex SoCs compared to otherdesigns. The wires and the links of the NOC are shared by many signals.A high level of parallelism is achieved because all links in the NOC canoperate simultaneously on different data packets. Therefore, as thecomplexity of integrated subsystems keep growing, a NOC providesenhanced performance (such as throughput) and scalability in comparisonwith previous communication architectures (e.g., dedicatedpoint-to-point signal wires, shared buses, or segmented buses withbridges). In other embodiments, NOC 154 can be replaced by a bus.Connected to and in communication with NOC 154 is processor 156, ECCengine 158, memory interface 160, and DRAM controller 164. DRAMcontroller 164 is used to operate and communicate with local high speedvolatile memory 140 (e.g., DRAM). In other embodiments, local high speedvolatile memory 140 can be SRAM or another type of volatile memory.

ECC engine 158 performs error correction services. For example, ECCengine 158 performs data encoding and decoding, as per the implementedECC technique. In one embodiment, ECC engine 158 is an electricalcircuit programmed by software. For example, ECC engine 158 can be aprocessor that can be programmed. In other embodiments, ECC engine 158is a custom and dedicated hardware circuit without any software. Inanother embodiment, the function of ECC engine 158 is implemented byprogramming processor 156.

Processor 156 performs the various operations, such as programming,erasing, reading, as well as memory management processes. In oneembodiment, processor 156 is programmed by firmware. In otherembodiments, processor 156 is a custom and dedicated hardware circuitwithout any software. Processor 156 also implements a translationmodule, as a software/firmware process or as a dedicated hardwarecircuit. In many systems, the non-volatile memory is addressedinternally to the storage system using physical addresses associatedwith the one or more memory die. However, the host system will uselogical addresses to address the various memory locations. This enablesthe host to assign data to consecutive logical addresses, while thestorage system is free to store the data as it wishes among thelocations of the one or more memory die. To implement this system, thecontroller (e.g., the translation module) performs address translationbetween the logical addresses used by the host and the physicaladdresses used by the memory dies. One example implementation is tomaintain tables (i.e. the L2P tables mentioned above) that identify thecurrent translation between logical addresses and physical addresses. Anentry in the L2P table may include an identification of a logicaladdress and corresponding physical address. Although logical address tophysical address tables (or L2P tables) include the word “tables” theyneed not literally be tables. Rather, the logical address to physicaladdress tables (or L2P tables) can be any type of data structure. Insome examples, the memory space of a storage system is so large that thelocal memory 140 cannot hold all of the L2P tables. In such a case, theentire set of L2P tables are stored in a memory die 130 and a subset ofthe L2P tables are cached (L2P cache) in the local high speed volatilememory 140.

Memory interface 160 communicates with one or more integrated memoryassemblies 130. In one embodiment, memory interface 160 provides aToggle Mode interface. Other interfaces can also be used. In someexample implementations, memory interface 160 (or another portion ofcontroller 120) implements a scheduler and buffer for transmitting datato and receiving data from one or more memory die.

FIG. 2 is a functional block diagram of one embodiment of an integratedmemory assembly 130. In one embodiment, the integrated memory assembly130 includes two semiconductor die (or more succinctly, “die”): memorydie 302 and control die 304. In some embodiments, the memory die 302 andthe control die 304 are directly connected or bonded together, as willbe described in more detail below. For purposes of this document, thephrases directly connected and directly bonded refer to the memory diebeing connected/bonded to the control die with no other die between thememory die and the control die. Herein, the term, “memory die,” “memorysemiconductor die,” or the like, means a semiconductor die that containsnon-volatile memory cells for storage of data. Herein, the term,“control die,” “control semiconductor die,” or the like, means asemiconductor die that contains control circuitry for performing memoryoperations on non-volatile memory cells on a memory die.

Memory die 302 includes include memory structure 326. Memory structure326 includes non-volatile memory cells. In one embodiment, memorystructure 326 comprises a monolithic three dimensional memory array ofnon-volatile memory cells in which multiple memory levels are formedabove a single substrate, such as a wafer. The memory structure maycomprise any type of non-volatile memory that is monolithically formedin one or more physical levels of arrays of memory cells having anactive area disposed above a silicon (or other type of) substrate. Inone example, the non-volatile memory cells of memory structure 326comprise vertical NAND strings with charge-trapping material such asdescribed, for example, in U.S. Pat. No. 9,721,662, incorporated hereinby reference in its entirety. A NAND string includes memory cellsconnected by a channel.

In another embodiment, memory structure 326 comprises a two dimensionalmemory array of non-volatile memory cells. In one example, thenon-volatile memory cells are NAND flash memory cells utilizing floatinggates such as described, for example, in U.S. Pat. No. 9,082,502,incorporated herein by reference in its entirety. Other types of memorycells (e.g., NOR-type flash memory) can also be used.

The exact type of memory array architecture or memory cell included innon-volatile memory structure 326 is not limited to the examples above.Many different types of memory array architectures or memory celltechnologies can be used to form memory structure 326. No particularnon-volatile memory technology is required for purposes of the newclaimed embodiments proposed herein. Other examples of suitabletechnologies for memory cells of the memory structure 326 includeferroelectric memories (FeRAM or FeFET), ReRAM memories,magnetoresistive memory (e.g., MRAM, Spin Transfer Torque MRAM, SpinOrbit Torque MRAM), phase change memory (e.g., PCM), and the like.Examples of suitable technologies for architectures of memory structure326 include two dimensional arrays, three dimensional arrays,cross-point arrays, stacked two dimensional arrays, vertical bit linearrays, and the like.

A person of ordinary skill in the art will recognize that the technologydescribed herein is not limited to a single specific memory structure,but covers many relevant memory structures within the spirit and scopeof the technology as described herein and as understood by one ofordinary skill in the art.

For purposes of this document, a control circuit is an electricalcircuit that is used to control or manage non-volatile memory. In oneembodiment, memory die 302 includes a control circuit positioned on thesilicon substrate of memory die 302 and non-volatile memory structure326 is positioned directly above the control circuit on the siliconsubstrate of memory die 302. Thus, the control circuit on the siliconsubstrate of memory die 302 is referred to as being under the memoryarray. In one embodiment, the control circuit on the silicon substrateof memory die 302 comprises read/write circuits 340 and controlcircuitry 342, both of which will be explained in more detail below.

Control die 304 includes control circuitry 310 positioned on the siliconsubstrate of control die 304. In one embodiment, control circuitry 310is an example of a control circuit for memory structure 326. Controlcircuitry 310 comprises a set of electrical circuits that perform memoryoperations (e.g., program, read, erase and others) on memory structure326. In some embodiments, “writing” refers to programming. In someembodiments, “writing” also refers to erasing. Some embodiments utilizethe concept of writing without referring to programming and erasing.

Control circuitry 310 includes state machine 312, an on-chip addressdecoder 314, a power control circuit 316, storage region 318, read/writecircuits 328, ECC engine 330, memory controller interface 332, andmemory die interface 340. State machine 312 is an electrical circuitthat controls the operations performed by control die 304. In someembodiments, state machine 312 is implemented by or replaced by amicroprocessor, microcontroller and/or RISC processor. Storage region318 can be volatile memory used to store software for programming aprocessor (e.g., the RISC processor used to implement or replace statemachine 312) and for storing data (e.g., data for the decoding processand encoding process and operational parameters). In one embodiment,storage region 312 is implemented with SRAM or DRAM.

The on-chip address decoder 314 provides an address interface betweenaddresses used by host 120 or memory controller 120 to the hardwareaddress used by row decoders and column decoders (not expressly depictedin FIG. 2). Power control circuit 316 controls the power and voltagessupplied to the word lines, bit lines, and select lines during memoryoperations. The power control circuit 316 includes voltage circuitry, inone embodiment. Power control circuit 316 may include charge pumps, highvoltage pumps or other voltage sources for creating voltages. The powercontrol circuit 316 executes under control of the state machine 312.

Read/write circuits 328 includes sense blocks, which may contain senseamplifiers. The sense amplifies include bit line drivers. The read/writecircuits 328 execute under control of the state machine 312. Each memorystructure 326 is addressable by word lines by way of a row decoder (notdepicted in FIG. 2) and by bit lines by way of a column decoder (notdepicted in FIG. 2).

Error correction code (ECC) engine 330 is a circuit configured to decodeand error correct codewords. Herein, ECC engine 330 may be referred toas an on-die ECC engine. In one embodiment, the on-die ECC engine 330 isconfigured to encode data bits from memory controller 120 into codewordsthat contain the data bits and parity bits. The control circuitry storesthe codewords in the memory structure 326. In one embodiment, the on-dieECC engine 330 is also configured to decode the codewords which are readfrom the memory structure 326. In some embodiments, if the on-die ECCengine 330 is successful at decoding a codeword, then the control die304 only sends back the data bits to the memory controller 120. In someembodiments, if the on-die ECC engine 330 is not successful at decodinga codeword, then the memory controller's ECC engine may be used todecode the codeword.

In one embodiment, all or a subset of the circuits of control circuitry310 (collectively or individually) can be considered a control circuit.The control circuit can include hardware only (e.g., electricalcircuits) or a combination of hardware and software (includingfirmware). For example, a controller programmed by firmware is oneexample of a control circuit. The control circuit can include aprocessor, PGA (Programmable Gate Array, FPGA (Field Programmable GateArray), ASIC (Application Specific Integrated Circuit), microcontroller,integrated circuit or other type of circuit.

Memory interface 340 is an electrical interface between control die 304and memory doe 302, employing pathways 344. Pathways 344 are pathwaysbetween one or more components in the control circuitry 310 and thecomponents (e.g., memory structure 326, read/write circuits 340 andcontrol circuitry 342) on memory die 302. A portion of each pathwayresides in memory die 302 and a portion of each pathway resides incontrol die 304. The term pathway may be used for a portion of pathways344 that is entirely within one of the die. Thus, it may be stated thatthe memory die 302 has a first plurality of pathways and that thecontrol die 304 has a second plurality of pathways such that the firstplurality of pathways are directly connected to the second plurality ofpathways (e.g., no intervening pathways). In one embodiment, the controldie 304 and the memory die 302 are configured to transfer signalsthrough pathway pairs of the first plurality of pathways and the secondplurality of pathways. In some embodiments, the memory die 302 and thecontrol die 304 are bonded to each other, or otherwise attached to eachother, to facilitate signal transfer through the pathway pairs.

A pathway may be used to provide or receive a signal (e.g., voltage,current). A pathway includes an electrically conductive path. A pathwaymay include one or more of, but is not limited to, a bond pad, metalinterconnect, via, transistor, electrically conducting material andother material that may transfer or carry an electrical signal. In oneembodiment, pathways 344 allow the control circuitry 310 to providevoltages to word lines, select lines, and bit lines on memory die 302.Pathways 344 may be used to receive signals from, for example, bitlines. In one embodiment, there are about 100,000 pathways 344. However,there could be more or fewer than 100,000 pathways. Having such a largenumber of pathways 344 allows a very large amount of data, or othersignals, to be passed in parallel.

Memory controller interface 332 is an electrical interface forcommunicating with memory controller 120. For example, memory controllerinterface 332 may implement a Toggle Mode Interface that connects tomemory controller 120. Memory interface 340 is significantly wider thanmemory controller interface 332 because memory interface 340 hassignificantly more signals than memory controller interface 332.Therefore, more data can be sent in parallel for memory interface 340 ascompared to memory controller interface 332. In some examples, memoryinterface 340 is 4×, 10×, 20×, or 50× wider than memory controllerinterface 332.

Communication channel 336 is depicted as being connected to integratedmemory assembly 130 for generality. Communication channel 336 mayconnect to either or both of die 302 and/or 304. In one embodiment,communication channel 336 connects memory controller 120 directly tocontrol die 304. In one embodiment, communication channel 336 connectsmemory controller 120 directly to memory die 302. If communicationchannel 336 connects memory controller 120 directly to memory die 302,then pathways 344 may be used to allow communication between memorycontroller 120 and control circuitry 310.

Although FIG. 2 depicts one control die 304 and one memory die 302 in anintegrated memory assembly 130, there may be more than one control die304 and more than one memory die 302 in an integrated memory assembly130.

FIG. 3 is a block diagram of one embodiment of the read/write circuits328 and ECC engine 330 of the control die 304. The read/write circuits328 have sense amplifiers 350 and latches 352. The latches 352 mayinclude data latches 354 a and parity latches 354 b. In one embodiment,the data latches 354 a store data bits of the codeword and the paritylatches store parity bits of the codeword. It is not required that therebe specific latches for data bits and for parity bits. FIG. 3 depictsfour sets of data latches 354(1), 354(2), 354(3), 354(4). Each set maybe used to store a codeword for a different page. In an embodiment inwhich four bits are stored per memory cell, four pages are stored in aset of memory cells. The four pages may be referred to as a lower page(LP), lower-middle page (LMP), upper-middle page (UMP), and an upperpage (UP). In an embodiment in which three bits are stored per memorycell, three pages are stored in a set of memory cells and the four pagesmay be referred to as a lower page (LP), middle page (MP), and an upperpage (UP).

The on-die ECC engine 330 is able to encode data bits received frommemory controller 120. In one embodiment, the on-die ECC engine 330forms codewords that each contain data bits and parity bits. In oneembodiment, memory controller 120 provides the codewords to the controldie 304. Control circuitry 310 stores the codewords into non-volatilememory cells in the memory structure 326. Upon a request from memorycontroller 120 to read data, control circuitry 310 reads codewords frommemory structure 326. The on-die ECC engine 330 is also able to decodeand error correct the codewords read from the memory structure 326. Insome embodiments, the on-die ECC engine 330 calculates parity bits foreach unit of data (e.g., page) that is being stored. The parity bits(also referred to as an error correction code or error correctioninformation) may be stored with the unit of data (e.g., page). Thecombination of the unit of data and its associated parity bits arereferred to as a codeword. In one embodiment, the parity bits are storedremotely from the unit of data (e.g., page).

In one embodiment, upon successfully decoding a codeword, control die304 sends only the data bits, but not the parity bits, to memorycontroller 120. Therefore, bandwidth over communication lines betweenmemory controller 120 and the integrated memory assembly 130 is saved.Also, substantial power may be saved. For example, the interface betweenthe control die and the controller could be a high speed interface.

The on die ECC engine 330 includes syndrome calculation logic 356, anencoder 358, and a decoder 394. The encoder 380 is configured to encodedata using an ECC scheme, such as a low-density parity check (LDPC)encoder, a Reed Solomon encoder, a Bose-Chaudhuri-Hocquenghem (BCH)encoder, a Turbo Code encoder, an encoder configured to encode one ormore other ECC encoding schemes, or any combination thereof. The encoder380 may form a codeword, which contains data bits 360 and parity bits362. The data bits may be provided by memory controller 120.

Based on the bits in the latches 352, the sense amplifiers 350 maycontrol bit line voltages in the memory structure 326 when thenon-volatile memory cells are being programmed/written. In this manner,the codewords may be programmed into non-volatile memory cells in thememory structure 326. It will be appreciated that other voltages mayalso be applied to the memory structure 326, such applying a programvoltage to memory cells that are selected for programming by a voltagegenerator on control die 304 applying the program voltage and boostingvoltages to various word lines of memory structure 326.

Decoder 364 is configured to decode the codewords that were stored inthe memory die 302. In one embodiment, sense amplifiers 350 sense bitlines in the memory structure 326 in order to read a codeword. The senseamplifiers 350 may store the read codeword into latches 352. The decoder364 is able to detect and correct errors in the codeword. In oneembodiment, the decoder 364 is a relatively low power decoder, ascompared to a decoder on memory controller 120. In one embodiment, thedecoder on memory controller 120 is able to correct more bit errors inthe codeword than can typically be corrected by decoder 364. Thus,decoder 364 may provide a power versus error correction capabilitytradeoff. For example, decoder 364 may be very efficient with respect topower consumption, but at the expense of possibly not being able tocorrect a high number of errors in a codeword.

In some embodiments, decoder 364 is based on a sparse bipartite graphhaving bit (or variable) nodes and check nodes. The decoder 364 may passmessages between the bit nodes and the check nodes. Passing a messagebetween a bit node and a check node is accomplished by performing amessage passing computation. The message passing computation may bebased on belief propagation.

Syndrome calculation logic 356 (e.g., an electrical circuit and/orsoftware) is able to determine a syndrome weight for codewords. Thesyndrome weight refers to the number of parity check equations that areunsatisfied. The initial syndrome weight of a codeword may correlatewith the bit error rate (BER) of that codeword. Thus, the control die304 may estimate a BER for a codeword based on the initial syndromeweight. In one embodiment, the syndrome logic is implemented inhardware. The syndrome weight can be determined without fully decoding acodeword. Hence, the initial syndrome weight can be calculated in lesstime and with less power than for decoding a codeword. In someembodiments, control die 304 makes management decisions based on theestimated BER. For example, control die 304 may determine what techniqueshould be used to decode a codeword, what read reference voltages shouldbe used to read memory cells, etc. based on the estimated BER.

FIG. 4 is a block diagram depicting one embodiment of a sense block 370,which is part of the read/write circuits 328. An individual sense block450 is partitioned into one or more core portions, referred to as sensecircuits or sense amplifiers 350(1)-350(4), and a common portion,referred to as a managing circuit 371. In one embodiment, there will bea separate sense circuit for each bit line/NAND string and one commonmanaging circuit 371 for a set of multiple, e.g., four or eight, sensecircuits. Each of the sense circuits in a group communicates with theassociated managing circuit by way of data bus 372. Thus, there are oneor more managing circuits which communicate with the sense circuits of aset of storage elements (memory cells).

The sense amplifier 350(1), as an example, comprises sense circuitry 373that performs sensing by determining whether a conduction current in aconnected bit line is above or below a predetermined threshold level.The sensing can occur in a read or verify operation. The sense circuitalso supplies a bit line voltage during the application of a programvoltage in a program operation (e.g., write operation).

The sense circuitry 373 may include a Vbl selector 374, a sense node375, a comparison circuit 376 and a trip latch 377. During theapplication of a program voltage, the Vbl selector 374 can pass aprogram enable voltage (e.g., V_pgm_enable) or a program-inhibit voltage(e.g., Vbl_inh) to a bit line connected to a memory cell. The Vblselector 374 can also be used during sensing operations. Herein, a“program enable voltage” is defined as a voltage applied to a memorycell that enables programming of the memory cell while a program voltage(e.g., Vpgm) is also applied to the memory cell. In certain embodiments,a program enable voltage is applied to a bit line coupled to the memorycell while a program voltage is applied to a control gate of the memorycell. Herein, a “program inhibit voltage” is defined as a voltageapplied to a bit line coupled to a memory cell to inhibit programming ofthe memory cell while a program voltage (e.g., Vpgm) is also applied tothe memory cell (e.g., applied to the control gate of the memory cell).Note that boosting voltages (e.g., Vpass) may be applied to unselectedword lines along with the program inhibit voltage applied to the bitline. The bit lines are part of memory structure 326 on memory die 302.

Program inhibit voltages are applied to bit lines coupled to memorycells that are not to be programmed and/or bit lines having memory cellsthat have reached their respective target threshold voltage throughexecution of a programming process. These may be referred to as“unselected bit lines.” Program inhibit voltages are not applied to bitlines (“selected bit lines”) having a memory cell to be programmed. Whena program inhibit voltage is applied to an unselected bit line, the bitline is cut off from the NAND channel, in one embodiment. Hence, theprogram inhibit voltage is not passed to the NAND channel, in oneembodiment. Boosting voltages are applied to unselected word lines toraise the potential of the NAND channel, which inhibits programming of amemory cell that receives the program voltage at its control gate.

A transistor 380 (e.g., an nMOS) can be configured as a pass gate topass Vbl from the Vbl selector 374, by setting the control gate voltageof the transistor sufficiently high, e.g., higher than the Vbl passedfrom the Vbl selector. For example, a selector 379 may pass a powersupply voltage Vdd, e.g., 3-4 V to the control gate of the transistor380.

The sense amplifier 350(1) is configured to control the timing of whenthe voltages are applied to the bit line. During sensing operations suchas read and verify operations, the bit line voltage is set by thetransistor 380 based on the voltage passed by the selector 379. The bitline voltage is roughly equal to the control gate voltage of thetransistor minus its Vt (e.g., 3 V). For example, if Vbl+Vt is passed bythe selector 379, the bit line voltage will be Vbl. This assumes thesource line is at 0 V. The transistor 380 clamps the bit line voltageaccording to the control gate voltage and acts as a source-followerrather than a pass gate. The Vbl selector 374 may pass a relatively highvoltage such as Vdd which is higher than the control gate voltage on thetransistor 380 to provide the source-follower mode. During sensing, thetransistor 380 thus charges up the bit line.

In one approach, the selector 379 of each sense amplifier can becontrolled separately from the selectors of other sense amplifiers, topass Vbl or Vdd. The Vbl selector 462 of each sense amplifier can alsobe controlled separately from the Vbl selectors of other senseamplifiers.

During sensing, the sense node 375 is charged up to an initial voltagesuch as Vsense_init=3 V. The sense node is then connected to the bitline by way of the transistor 380, and an amount of decay of the sensenode is used to determine whether a memory cell is in a conductive ornon-conductive state. In one embodiment, a current that flows in the botline discharges the sense node (e.g., sense capacitor). The length oftime that the sense node is allowed to decay may be referred to hereinas an “integration time.” The comparison circuit 466 is used to comparethe sense node voltage to a trip voltage at a sense time. If the sensenode voltage decays below the trip voltage Vtrip, the memory cell is ina conductive state and its Vt is at or below the voltage of theverification signal. If the sense node voltage does not decay belowVtrip, the memory cell is in a non-conductive state and its Vt is abovethe voltage of the verification signal. The sense amplifier 350(1)includes a trip latch 468 that is set by the comparison circuit 466based on whether the memory cell is in a conductive or non-conductivestate. The data in the trip latch can be a bit which is read out by theprocessor 381.

The managing circuit 371 comprises a processor 381, four example sets ofdata latches 382, 383, 384, 385 and an I/O Interface 387 coupled betweenthe sets of data latches and data bus 332 (data bus may connect tomemory controller 102). One set of data latches, e.g., comprisingindividual latches LDL, LMDL, UMDL, and UDL, can be provided for eachsense amplifier. In some cases, fewer or additional data latches may beused. LDL stores a bit for a lower page of data, LMDL stores a bit for alower-middle page of data, UMDL stores a bit for an upper-middle page ofdata, and UDL stores a bit for an upper page of data. This is in asixteen level or four bits per memory cell memory device. In oneembodiment, there are eight levels or three bits per memory cell and,therefore, only three latches (LDL, MDL, UDL) per sense amplifier.

The processor 381 performs computations, such as to determine the datastored in the sensed memory cell and store the determined data in theset of data latches. Each set of data latches 382-385 is used to storedata bits determined by processor 381 during a read operation, and tostore data bits imported from the data bus 332 during a programoperation which represent write data meant to be programmed into thememory. I/O interface 488 provides an interface between data latches382-385 and the data bus 332.

The processor 381 may also be used to determine what voltage to apply tothe bit line, based on the state of the latches.

During reading, the operation of the system is under the control ofstate machine 312 that controls the supply of different control gatevoltages to the addressed memory cell (e.g., by applying voltages frompower control 316 to word lines on the memory structure 326 by way ofthe pathways between control die 304 and memory die 302 discussedherein). As it steps through the various predefined control gatevoltages corresponding to the various memory states supported by thememory, the sense circuit may trip at one of these voltages and acorresponding output will be provided from sense circuit to processor482 by way of the data bus 454. At that point, processor 482 determinesthe resultant memory state by consideration of the tripping event(s) ofthe sense circuit and the information about the applied control gatevoltage from the state machine by way of input lines 490. It thencomputes a binary encoding for the memory state and stores the resultantdata bits into data latches 484-487.

Some implementations can include multiple processors 381. In oneembodiment, each processor 381 will include an output line (notdepicted) such that each of the output lines is wired-OR'd together. Insome embodiments, the output lines are inverted prior to being connectedto the wired-OR line. This configuration enables a quick determinationduring a program verify test of when the programming process hascompleted because the state machine receiving the wired-OR can determinewhen all bits being programmed have reached the desired level. Forexample, when each bit has reached its desired level, a logic zero forthat bit will be sent to the wired-OR line (or a data one is inverted).When all bits output a data 0 (or a data one inverted), then the statemachine knows to terminate the programming process. Because (in oneembodiment) each processor communicates with four sense amplifiers, thestate machine needs to read the wired-OR line four times, or logic isadded to processor 381 to accumulate the results of the associated bitlines such that the state machine need only read the wired-OR line onetime. Similarly, by choosing the logic levels correctly, the globalstate machine can detect when the first bit changes its state and changethe algorithms accordingly.

During program or verify operations for memory cells, the data to beprogrammed (write data) is stored in the set of data latches 382-385from the data bus 332, in the LDL, LMDL, UMDL, and UDL latches, in afour-bit per memory cell implementation.

The program operation, under the control of the state machine, applies aset of programming voltage pulses to the control gates of the addressedmemory cells. Each voltage pulse may be stepped up in magnitude from aprevious program pulse by a step size in a process referred to asincremental step pulse programming. Each program voltage is followed bya verify operation to determine if the memory cells has been programmedto the desired memory state. In some cases, processor 381 monitors theread back memory state relative to the desired memory state. When thetwo are in agreement, the processor 381 sets the bit line in a programinhibit mode such as by updating its latches. This inhibits the memorycell coupled to the bit line from further programming even if additionalprogram pulses are applied to its control gate.

Each set of data latches 382-385 may be implemented as a stack of datalatches for each sense amplifier. In one embodiment, there are threedata latches per sense amplifier 350. In some implementations, the datalatches are implemented as a shift register so that the parallel datastored therein is converted to serial data for data bus 332, and viceversa. All the data latches corresponding to the read/write block ofmemory cells can be linked together to form a block shift register sothat a block of data can be input or output by serial transfer. Inparticular, the bank of read/write circuits is adapted so that each ofits set of data latches will shift data in to or out of the data bus insequence as if they are part of a shift register for the entireread/write block.

The data latches identify when an associated memory cell has reachedcertain milestones in a program operation. For example, latches mayidentify that a memory cell's Vt is below a particular verify voltage.The data latches indicate whether a memory cell currently stores one ormore bits from a page of data. For example, the LDL latches can be usedto store a lower page of data. An LDL latch is flipped (e.g., from 0to 1) when a lower page bit is stored in an associated memory cell. AnLMDL, UMDL or UDL latch is flipped when a lower-middle, upper-middle orupper page bit, respectively, is stored in an associated memory cell.This occurs when an associated memory cell completes programming.

In one embodiment, memory structure 326 includes a pluralitynon-volatile memory cells arranged as vertical NAND strings. Forexample, the memory structure may include a stack of alternatingdielectric layers and conductive layers, with memory holes formed in thestack. NAND strings are formed by filling the memory holes withmaterials including a charge-trapping material to create a verticalcolumn of memory cells. Each memory cell can store one or more bits ofdata. More details of the three dimensional monolithic memory array thatcomprises memory structure 326 is provided below with respect to FIGS.4-12.

FIG. 5 is a block diagram explaining one example organization of memorystructure 326, which is divided into four planes P0. P1, P2 and P3. Eachplane is then divided into M blocks. In one example, each plane hasabout 2000 blocks. However, different numbers of blocks and planes canalso be used. In on embodiment, a block of memory cells is a unit oferase. That is, all memory cells of a block are erased together.Therefore, a block may also be referred to as an erase block. In otherembodiments, memory cells can be grouped into blocks for other reasons,such as to organize the memory structure 326 to enable the signaling andselection circuits. In some embodiments, a block represents a groups ofconnected memory cells as the memory cells of a block share a common setof word lines.

FIGS. 6-9 depict an example three dimensional (“3D”) NAND structure thatcan be used to implement memory structure 326. FIG. 6 is a block diagramdepicting a top view of a portion of one block from memory structure326. The portion of the block depicted in FIG. 6 corresponds to portion401 in Block 2 of FIG. 5. As can be seen from FIG. 6, the block depictedin FIG. 6 extends in the direction of 431. In one embodiment, the memoryarray has many layers; however, FIG. 6 only shows the top layer.

FIG. 6 depicts a plurality of circles that represent the verticalcolumns. Each of the vertical columns include multiple selecttransistors (also referred to as a select gate or selection gate) andmultiple memory cells. In one embodiment, each vertical columnimplements a NAND string. For example, FIG. 6 depicts vertical columns422, 432, 442 and 452. Vertical column 422 implements NAND string 482.Vertical column 432 implements NAND string 484. Vertical column 442implements NAND string 486. Vertical column 452 implements NAND string488. More details of the vertical columns are provided below. Since theblock depicted in FIG. 6 extends in the direction of arrow 431, theblock includes more vertical columns than depicted in FIG. 6.

FIG. 6 also depicts a set of bit lines 415, including bit lines 411,412, 413, 414, . . . 419. FIG. 6 shows twenty four bit lines becauseonly a portion of the block is depicted. It is contemplated that morethan twenty four bit lines connected to vertical columns of the block.Some of the circles representing vertical columns has an “x” to indicateits connection to one bit line. For example, bit line 414 is connectedto vertical columns 422 and 432. The block depicted in FIG. 6 includes aset of full slits 402 and 410 that are etched from the top of thevertical columns to the bottom of the vertical columns, and filled withoxide. Partial slits 404, 406, and 408 are etched through the top oflayers to divide the select lines, as described below, in order todivide each layer of the block into four regions (420, 430, 440, and450) that are referred to as sub-blocks (and will be discussed in moredetail below). In one example implementation, a bit line only connectsto (at most) one vertical column in each of sub-blocks 420, 430, 440 and450. In that implementation, each block has sixteen rows of activecolumns and each bit line connects to two rows in each block. In oneembodiment, all of two rows connected to a common bit line are connectedto the same word line but different select lines; therefore, the systemuses the source side selection lines and the drain side selection linesto choose one (or another subset) of the four to be subjected to amemory operation. Although FIG. 6 shows each region having four rows ofvertical columns, four regions and sixteen rows of vertical columns in ablock, those exact numbers are an example implementation. Otherembodiments may include more or less regions per block, more or lessrows of vertical columns per region and more or less rows of verticalcolumns per block. FIG. 6 also shows the vertical columns beingstaggered. In other embodiments, different patterns of staggering can beused. In some embodiments, the vertical columns are not staggered.

FIG. 7 depicts a portion of one embodiment of a three dimensional memorystructure 326 showing a cross-sectional view along line AA of FIG. 6.This cross sectional view cuts through vertical columns 432 and 434 andregion/sub-block 430 (see FIG. 6). The structure of FIG. 7 includes fourtop side select layers TSGL0, TSGL1, TSGL2 and TSGL3; four bottom sideselect layers BSGL0, BSGL1, BSGL2 and BSGL3; six dummy word line layersDD0, DD1, DS0, DS1, WLDL, WLDU; and ninety six data word line layersWLL0-WLL95 for connecting to data memory cells. Other embodiments canimplement more or less than four top side side select layers, more orless than four bottom side select layers, more or less than six dummyword line layers, and more or less than ninety six word lines. Verticalcolumns 432 and 434 are depicted protruding through the top side selectlayers, source side select layers, dummy word line layers and word linelayers. In one embodiment, each vertical column comprises a verticalNAND string. For example, vertical column 432 comprises NAND string 484.Directly below the vertical columns and the layers listed below is acontrol circuit (not depicted in FIG. 7), and directly below the controlcircuit is a substrate (not depicted), For purposes of this document,the phrase “directly below” means underneath rather than to the side.The NAND string of vertical column 432 has a source end at a bottom ofthe stack and a drain end at a top of the stack. As in agreement withFIG. 6, FIG. 6 shows vertical column 432 connected to Bit Line 414 viaconnector 417. Local interconnects 404 and 406 are also depicted.

For ease of reference, top side select layers TSGL0, TSGL1, TSGL2 andTSGL3; bottom side select layers BSGL0, BSGL1, BSGL2 and BSGL3; dummyword line layers DD0, DD1, DS0, DS1, WLDL and WLDU; and word line layersWLL0-WLL95 collectively are referred to as the conductive layers. In oneembodiment, the conductive layers are made from a combination of TiN andTungsten. In other embodiments, other materials can be used to form theconductive layers, such as doped polysilicon, metal such as Tungsten ormetal silicide. In some embodiments, different conductive layers can beformed from different materials. Between conductive layers aredielectric layers DL0-DL111. For example, dielectric layers DL104 isabove word line layer WLL94 and below word line layer WLL95. In oneembodiment, the dielectric layers are made from SiO₂. In otherembodiments, other dielectric materials can be used to form thedielectric layers.

The non-volatile memory cells are formed along vertical columns whichextend through alternating conductive and dielectric layers in thestack. In one embodiment, the memory cells are arranged in NAND strings.The word line layers WLL0-WLL95 connect to memory cells (also calleddata memory cells). Dummy word line layers DD0, DD1, DS0, DS1, WLDL andWLDU connect to dummy memory cells. A dummy memory cell does not storeand is not eligible to store host data (data provided from the host,such as data from a user of the host), while a data memory cell iseligible to store host data. In some embodiments, data memory cells anddummy memory cells may have a same structure. A dummy word line isconnected to dummy memory cells. Top side select layers TSGL0, TSGL1,TSGL2 and TSGL3 are used to electrically connect and disconnect NANDstrings from bit lines or source lines (as discussed below). Bottom sideselect layers BSGL0, BSGL1, BSGL2 and BSGL3 are used to electricallyconnect and disconnect NAND strings from source lines or bit lines (asdiscussed below).

FIG. 7 also shows a Joint area. In one embodiment it is expensive and/orchallenging to etch ninety six word line layers intermixed withdielectric layers. To ease this burden, one embodiment includes layingdown a first stack of forty eight word line layers alternating withdielectric layers, laying down the Joint area, and laying down a secondstack of forty eight word line layers alternating with dielectriclayers. The Joint area is positioned between the first stack and thesecond stack. The Joint area is used to connect to the first stack tothe second stack. In FIG. 7, the first stack is labeled as the “LowerSet of Word Lines” and the second stack is labeled as the “Upper Set ofWord Lines.” In one embodiment, the Joint area is made from the samematerials as the word line layers. In one example set ofimplementations, the plurality of word lines (control lines) comprises afirst stack of alternating word line layers and dielectric layers, asecond stack of alternating word line layers and dielectric layers, anda joint area between the first stack and the second stack, as depictedin FIG. 7.

FIG. 8 depicts a cross sectional view of region 429 of FIG. 7 thatincludes a portion of vertical column 432 (a memory hole). In oneembodiment, the vertical columns are round; however, in otherembodiments other shapes can be used. In one embodiment, vertical column432 includes an inner core layer 470 that is made of a dielectric, suchas SiO₂. Other materials can also be used. Surrounding inner core 470 ispolysilicon channel 471. Materials other than polysilicon can also beused. Note that it is the channel 471 that connects to the bit line andthe source line. Surrounding channel 471 is a tunneling dielectric 472.In one embodiment, tunneling dielectric 472 has an ONO structure.Surrounding tunneling dielectric 472 is charge trapping layer 473, suchas (for example) Silicon Nitride. Other memory materials and structurescan also be used. The technology described herein is not limited to anyparticular material or structure.

FIG. 8 depicts dielectric layers DLL105, DLL104, DLL103, DLL102 andDLL101, as well as word line layers WLL95, WLL94, WLL93, WLL92, andWLL91. Each of the word line layers includes a word line region 476surrounded by an aluminum oxide layer 477, which is surrounded by ablocking oxide layer 478. In other embodiments, the blocking oxide layercan be a vertical layer parallel and adjacent to charge trapping layer473. The physical interaction of the word line layers with the verticalcolumn forms the memory cells. Thus, a memory cell, in one embodiment,comprises channel 471, tunneling dielectric 472, charge trapping layer473, blocking oxide layer 478, aluminum oxide layer 477 and word lineregion 476. For example, word line layer WLL95 and a portion of verticalcolumn 432 comprise a memory cell MC1. Word line layer WLL94 and aportion of vertical column 432 comprise a memory cell MC2. Word linelayer WLL93 and a portion of vertical column 432 comprise a memory cellMC3. Word line layer WLL92 and a portion of vertical column 432 comprisea memory cell MC4. Word line layer WLL91 and a portion of verticalcolumn 432 comprise a memory cell MC5. In other architectures, a memorycell may have a different structure; however, the memory cell wouldstill be the storage unit.

When a memory cell is programmed, electrons are stored in a portion ofthe charge trapping layer 473 which is associated with the memory cell.These electrons are drawn into the charge trapping layer 473 from thechannel 471, through the tunneling dielectric 472, in response to anappropriate voltage on word line region 476. The threshold voltage (Vth)of a memory cell is increased in proportion to the amount of storedcharge. In one embodiment, the programming is achieved throughFowler-Nordheim tunneling of the electrons into the charge trappinglayer. During an erase operation, the electrons return to the channel orholes are injected into the charge trapping layer to recombine withelectrons. In one embodiment, erasing is achieved using hole injectioninto the charge trapping layer via a physical mechanism such as gateinduced drain leakage (GIDL).

As discussed above, the integrated memory assembly includes a firstcontrol circuit on the memory die (underneath memory structure 326) anda second control circuit on the control die such that the first controlcircuit is configured to be used to perform a memory operation on afirst subset of the non-volatile memory cells (e.g., first sub-block)while the second control circuit is configured to be used toconcurrently perform the same memory operation on a second subset of thenon-volatile memory cells (e.g., second sub-block of same block). FIG. 9is a cross sectional view of one embodiment of a portion of two blocksof memory cells (Block N and Block N+1) of memory structure 326 thatbetter explain how the various memory holes/NAND strings are connectedto the bit lines and source lines to enable the first control circuit toperform a memory operation on a first subset of the non-volatile memorycells while the second control circuit concurrently performs a memoryoperation on a second subset of the non-volatile memory cells. In oneembodiment, each block is divided into four sub-blocks SB0, SB1, SB2 andSB3. Sub-block SB0 corresponds to those vertical NAND strings controlledby TSGL0 and BSGL0, sub-block SB1 corresponds to those vertical NANDstrings controlled by TSGL1 and BSGL1, sub-block SB2 corresponds tothose vertical NAND strings controlled by TSGL2 and BSGL2, and sub-blockSB3 corresponds to those vertical NAND strings controlled by TSGL3 andBSGL3. For example purposes, and to make the drawing easier to read,FIG. 9 shows two memory holes/NAND strings for each sub-block (SB0, SB1,SB2, SB3) of Block N and Block N+1; however, in most embodiments eachsub-block will include more than two memory holes/NAND strings.

Memory structure 326 includes bit lines above memory structure 326 andbelow memory structure 326. For example, bit lines Top_BLn and Top_BLn+1are above memory structure 326, while bit lines Bottom_BLn andBottom_BLn+1 are below memory structure 326. It is contemplated thatthere will be more than two bit lines above memory structure 326 andmore than two bit lines below memory structure 326; however, FIG. 9 onlyshows two to make the drawing easier to read. In one embodiment, the topbit lines are connected to the control circuit (including senseamplifiers) of control die 304 (CCAA) and the bottom bit lines areconnected to the control circuit (including sense amplifiers) of memorydie 302 (CCUA). In the implementation depicted in FIG. 9, NAND stringsof sub-blocks SB0 and SB1 are connected to bit lines above the memorystructure and, thereby, to the sense amplifiers of control die 304(CCAA), while NAND strings of sub-blocks SB2 and SB3 are connected tobit lines below the memory structure and, thereby, to the senseamplifiers of memory die 302 (CCUA). For example, NAND string a ofsub-block SB0 is connected to Top_BLn, NAND string b of sub-block SB0 isconnected to Top_BLn+1, NAND string c of sub-block SB1 is connected toTop_BLn, NAND string d of sub-block SB1 is connected to Top_BLn+1, NANDstring e of sub-block SB2 is connected to Bottom_BLn, NAND string f ofsub-block SB2 is connected to Bottom_BLn+1, NAND string g of sub-blockSB3 is connected to Bottom_BLn, NAND string h of sub-block SB3 isconnected to Bottom_BLn+1, NAND string i of sub-block SB0 is connectedto Top_BLn, NAND string j of sub-block SB0 is connected to Top_BLn+1,NAND string k of sub-block SB1 is connected to Top_BLn, NAND string l ofsub-block SB1 is connected to Top_BLn+1, NAND string m of sub-block SB2is connected to Bottom_BLn, NAND string n of sub-block SB2 is connectedto Bottom_BLn+1, NAND string o of sub-block SB3 is connected toBottom_BLn, and NAND string p of sub-block SB3 is connected toBottom_BLn+1.

Memory structure 326 includes a source line (Top_SL) above memorystructure 326 and a source line (Bottom_SL) below memory structure 326.The source lines are shown as divided into individual and separatenon-continuous sections. Each of the individual sections of source lineTop_SL are connected together (e.g., shorted together or routed to acommon connection). Each of the individual sections of source lineBottom_SL are connected together (e.g., shorted together or routed to acommon connection). In one embodiment, Top_SL and Bottom_SL are bothconnected to the control circuit of control die 304. In anotherembodiment, Top_SL and Bottom_SL are both connected to the controlcircuit of memory die 302. In another embodiment, Top_SL is connected tothe control circuit of control die 304 and Bottom_SL is connected to thecontrol circuit of memory die 302.

In the arrangement of FIG. 9, a memory operation can be performed onNAND strings of sub-block SB0 (e.g., NAND strings a and b) via senseamplifiers on control die 304 (CCAA) while the memory operation isconcurrently performed on NAND strings of sub-block SB2 (e.g., NANDstrings e and f) via sense amplifiers on memory die 302 (CCUA); a memoryoperation can be performed on NAND strings of sub-block SB0 (e.g., NANDstrings a and b) via sense amplifiers on control die 304 while a memoryoperation is concurrently performed on NAND strings of sub-block SB3(e.g., NAND strings g and h) via sense amplifiers on memory die 302; amemory operation can be performed on NAND strings of sub-block SB1(e.g., NAND strings c and d) via sense amplifiers on control die 304while a memory operation is concurrently performed on NAND strings ofsub-block SB2 (e.g., NAND strings e and f) via sense amplifiers onmemory die 302; and a memory operation can be performed on NAND stringsof sub-block SB1 (e.g., NAND strings c and d) via sense amplifiers oncontrol die 304 while a memory operation is concurrently performed onNAND strings of sub-block SB3 (e.g., NAND strings g and h) via senseamplifiers on memory die 302.

In one example, the memory system can write a first page of data (e.g.,16 KB) to SB0 or SB1 via sense amplifiers on control die 304 whileconcurrently writing a second page of data to SB2 or SB3 via senseamplifiers on memory die 302, thus doubling the level of parallelismwhich results in an increase in speed/performance of the memory system.Similarly, the memory system can read a first page of data (e.g., 16 KB)from SB0 or SB1 via sense amplifiers on control die 304 whileconcurrently reading a second page of data to SB2 or SB3 via senseamplifiers on memory die 302, thus doubling the level of parallelismwhich results in an increase in speed/performance of the memory system.Additionally, since all of the memory cells of the two sub-blocksexperiencing a memory operation are connected to the same word line, theword line voltage (e.g., power) is being used more efficiently. That isthe same word line voltage will be used to write to twice as many memorycells or read from twice as many memory cells. Prior memory systemscould not achieve this level of parallelism because there was not enoughroom on a single die for enough sense amplifiers.

For purposes of this document, the term “concurrently” includesoverlapping in time, even if they start or stop at different times. Notethat FIG. 9 shows Top_BLn+1, Top_BLn, Top_SL and CCAA above the memorystructure, while Bottom_BLn, Bottom_BLn+1, Bottom SL and CCUA are belowthe memory structure. The terms above and below are used relative to thememory structure 326 and the substrate of memory die 302 such thatanything between memory structure 326 and the substrate of memory die302 is considered below the memory structure and anything that is on theopposite side of the memory structure than the substrate of memory die302 is considered above the memory structure, regardless of theorientation of the integrated memory assembly.

FIG. 9 shows top side selection line Top_SGL, which represents top sideselection lines TSGL0, TSGL1, TSGL2 and TSGL3; therefore, FIG. 9 depictsTop_SGL as four unconnected metal lines (with the same shading). FIG. 9also shows bottom side selection line Bottom_SGL, which representsbottom side selection lines BSGL0, BSGL1, BSGL2 and BSGL3; therefore,FIG. 9 depicts Bottom_SGL as four unconnected metal lines (with the sameshading). For NAND strings of sub-blocks SB0 and SB1 (e.g., a, b, c, d,i, j, k, l), Top_SGL operates as a drain side select line and Bottom_SGLoperates as a source side select line; therefore, the select gatesconnected to Top_SGL are drain side select gates and the select gatesconnected to Bottom_SGL are source side select gates. For NAND stringsof sub-blocks SB2 and SB3 (e.g., e, f, g, h, m, n, o, p), Top_SGLoperates as a source side select line and Bottom_SGL operates as a drainside select line; therefore, the select gates connected to Top_SGL aresource side select gates and the select gates connected to Bottom_SGLare drain side select gates. As such, the same selection line canconcurrently be a drain side selection line for some sub-blocks and asource side selection line for other sub-blocks.

FIG. 10 is a circuit diagram for the embodiment of FIG. 9, depicting aportion of the memory described in in FIGS. 5-8. Specifically, FIG. 10shows a portion of one block including NAND string a in sub-block SB0,NAND string c in sub-block SB1, NAND string e in sub-block SB2, NANDstring g in sub-block SB0, top bit lines (411, 412, 413, 414, 419),bottom bit lines (423, 425, 427, 429), Bottom_SL, and Top_SL. Top bitlines 411 and 412 correspond to bit lines Top_BLn and Top_BLn+1 of FIG.9. Bottom bit lines 423 and 425 correspond to bit lines Bottom_BLn andBottom_BLn+1 of FIG. 9. To make FIG. 10 easier to read, and for examplepurposes, only one NAND string is depicted for each of the sub-blocksSB0, SB1, SB2 and SB3. FIG. 10 shows physical word lines WLL0-WLL95running across the entire block. The structure of FIG. 10 corresponds toportion 401 in Block 2 of FIG. 5. Within the block, each bit line isconnected to two NAND strings. Top side selection lines TSGL0, TSGL1,TSGL2 and TSGL3 and bottom side selection lines BSGL0, BSGL1, BSGL2 andBSGL3 are used to determine which of the NAND strings connect to theassociated bit lines and source line(s).

FIG. 11 is a cross sectional view of one embodiment of a portion of twoblocks of memory cells. The structure of FIG. 11 is similar to thestructure of FIG. 9, except that the source lines (Top_SL and Bottom_SL)are continuous rather than divided into separate non-continuous sections(as depicted in FIG. 9). In the structure of FIG. 11, the source lines(Top_SL and Bottom_SL) will have been etched (e.g., a hole is etchedthrough the source lines) to allow the bit line contacts (and dielectricsurrounding the bit line contacts) to pass through the source lines.

As discussed above, NAND strings in half of the sub-blocks of a blockare connected to sense amplifiers above the memory structure (e.g., oncontrol die 304) and NAND strings in half of the sub-blocks of a blockare connected to sense amplifiers below the memory structure (e.g., onmemory die 302). In the embodiments of FIGS. 9 and 11, NAND strings ofSB0 and SB1 connect to sense amplifiers above the memory structure(e.g., on control die 304) and NAND strings of SB2 and SB3 connect tosense amplifiers below the memory structure (e.g., on memory die 302).FIG. 12 is a cross sectional view of another embodiment of a portion oftwo blocks of memory cells in which NAND strings of SB0 and SB2 connectto sense amplifiers above the memory structure (e.g., on control die304) and NAND strings of SB1 and SB3 connect to sense amplifiers belowthe memory structure (e.g., on memory die 302). Thus, in the embodimentof FIG. 12, NAND strings of SB0 and SB2 connect to bit lines (Top_BLnand Top_BLn+1) above the memory structure and connect to a source line(Bottom_SL) below the memory structure, while NAND strings of SB1 andSB3 connect to bit lines (Bottom_BLn and Bottom_BLn+1) below the memorystructure and connect to a source line (Top_SL) above the memorystructure. Therefore, a memory operation can be performed on SB0concurrently with either SB1 or SB3. Similarly, a memory operation canbe performed on SB2 concurrently with either SB1 or SB3.

FIGS. 12A and 12B include tables that identify example voltage biases toapply to top side selection lines TSGL0, TSGL1, TSGL2 and TSGL3(collectively Top_SGL) and bottom side selection lines BSGL0, BSGL1,BSGL2 and BSGL3 (collectively Bottom_SGL) in order to perform writingand reading of data. The table of FIG. 12A applies to the embodiment ofFIGS. 9-11. The table of FIG. 12B applies to the embodiment of FIG. 12.For example, the third column of FIG. 12A teaches to concurrentlyprogram/write to a NAND string in SB0 (e.g., NAND string a) and a NANDstring in SB2 (e.g., NAND string e), the systems applies VSGD to TSGL0,VSS to TSGL1, VSS to TSGL2, VSS to TSGL3, VSS to BSGL0, VSS to BSGL1,VSGD to BSGL2, and VSS to BSGL3. The voltage VSGD is equal toapproximately 2.5 volts. The voltage VSS is equal to approximately 0volts. The voltage VSG is equal to approximately 7 volts. Other voltagescan also be used, as per the specific implementation. Note that in thetable of FIG. 12B, even though a positive voltage is applied to Top_SGLand Bottom_SGL for a selected NAND strings, that selected NNAD stringcan be cut off from either the top or bottom by using an appropriatethreshold voltage for the transistor that is the select gate.

FIG. 13 is a block diagram depicting further details of one embodimentof an integrated memory assembly, depicting control die 304 bonded tomemory die 302. Control die includes a plurality of sense amplifiers350, a plurality of word line drivers 502(1) . . . 502(n), and othercircuits (not depicted in FIG. 13) that cumulatively form a controlcircuit. On the surface of the substrate of memory die 302 (and betweenthe substrate and the memory structure 326) is a plurality of senseamplifiers 350 and other control logic that that together form a controlcircuit. Memory die 302 includes at least one plane 530 of memory cells.Plane 530 is all or part of one example embodiment of memory structure326. Memory die 302 may have additional planes. The plane is dividedinto M blocks.

Each sense amplifier 350 is connected to one bit line. Tworepresentative bit lines (BL1 and BL2) are depicted for plane 530. Theremay be thousand or tens of thousands of such bit lines for each plane.Bit line BL1 is on top of plane 530, and is connected to a senseamplifier 350 on control die 304. Bit line BL2 is below plane 530, andis connected to a sense amplifier 350 on the memory die 302 (positionedon the substrate of memory die 302). The sense amplifiers contain bitline drivers. Thus, the sense amplifier may provide a voltage to the bitline to which it is connected. The sense amplifiers are also configuredto sense a condition of the bit line. In one embodiment, the senseamplifiers are configured to sense a current that flows in the bit line.In one embodiment, the sense amplifiers are configured to sense avoltage on the bit line.

The control die 304 includes a number of word line drivers502(1)-502(n). The word line drivers 560 are configured to providevoltages to word lines. In this example, there are “n” word lines perblock of memory cells. In one embodiment, one of the blocks in the plane530 is selected at a time for a memory array operation. If the memoryoperation is a program or read, one word line within the selected blockis selected for the memory operation, in one embodiment. If the memoryoperation is an erase, all of the word lines within the selected blockare selected for the erase, in one embodiment. The word line drivers 502(e.g. part of Power Control 316) provide voltages to the word lines in afirst selected block (e.g., Block 2) in memory die 302. The control die304 may also include charge pumps, voltage generators, and the like,which may be used to provide voltages for the word line drivers 502and/or the bit line drivers.

Memory die 302 has a number of bond pads 572 a, 572 b on a first majorsurface 586 of memory die 302. There may be “n” bond pads 572 a, toreceive voltages from a corresponding “n” word line drivers502(1)-502(n). There may be one bond pad 572 b for each bit lineassociated with plane 530. The reference numeral 572 will be used torefer in general to bond pads on major surface 586.

The control die 304 has a number of bond pads 576 a, 576 b on a firstmajor surface 588 of control die 304. There may be “n” bond pads 576 a,to deliver voltages from a corresponding “n” word line drivers502(1)-502(n) to memory die 302. There may be one bond pad 576 b foreach bit line associated with plane 530. The reference numeral 576 willbe used to refer in general to bond pads on major surface 588. Note thatthere may be bond pad pairs 572 a/576 a and bond pad pairs 572 b/572 b.In some embodiments, bond pads 570 and/or 574 are flip-chip bond pads(other types can also be used).

In one embodiment, the pattern of bond pads 572 matches the pattern ofbond pads 576. Bond pads 572 are bonded (e.g., flip chip bonded) to bondpads 576. Thus, the bond pads 572, 576 electrically and physicallycouple the memory die 302 to the control die 304. Also, the bond pads572, 576 permit internal signal transfer between the memory die 302 andthe control die 304. Thus, the memory die 302 and the control die 304are bonded together with bond pads. Although FIG. 13 depicts one controldie 304 bonded to one memory die 302, in another embodiment one controldie 304 is bonded to multiple memory dies 302.

Herein, “internal signal transfer” means signal transfer between thecontrol die 304 and the memory die 302. The internal signal transferpermits the circuitry on the control die 304 to control memoryoperations in the memory die 302 via the bond pads. Therefore, the bondpads 572, 576 may be used for memory operation signal transfer. A memoryoperation signal transfer could include, but is not limited to,providing a voltage, providing a current, receiving a voltage, receivinga current, sensing a voltage, and/or sensing a current.

The bond pads 572, 576 may be formed for example of copper, aluminum andalloys thereof. There may be a liner between the bond pads 572, 576 andthe major surfaces (586, 588). The liner may be formed for example of atitanium/titanium nitride stack. The bond pads 572, 576 and liner may beapplied by vapor deposition and/or plating techniques. The bond pads andliners together may have a thickness of 720 nm, though this thicknessmay be larger or smaller in further embodiments.

Metal interconnects and/or vias may be used to electrically connectvarious elements in the dies to the bond pads 572, 576. Severalconductive pathways, which may be implemented with metal interconnectsand/or vias are depicted. For example, a sense amplifier 350 may beelectrically connected to bond pad 576 b by a pathway. There may bethousands of such sense amplifiers, pathways, and bond pads. Note thatthe BL does not necessarily make direct connection to bond pad 572 b.The word line drivers 560 may be electrically connected to bond pads 576a by pathways 508. Note that pathways 508 may comprise a separateconductive pathway for each word line driver 502(1)-502(n). Likewise,there may be a separate bond pad 576 a for each word line driver502(1)-502(n). The word lines in block 2 of the memory die 302 may beelectrically connected to bond pads 572 a by pathways 508.

FIG. 14 is a block diagram depicting additional details of oneembodiment of an integrated memory assembly that includes memory die 302directly bonded to control die 304. This direct bonding configuration issimilar to the embodiment depicted in FIG. 13. Note that although a gapis depicted between the pairs of adjacent dies, such a gap may be filledwith an epoxy or other resin or polymer.

Memory structure 326 on memory die 302 includes a number of word linelayers (WL), which are separated by dielectric layers. The dielectriclayers are represented by gaps between the word line layers. Thus, theword line layers and dielectric layers form a stack. There may be manymore word line layers than are depicted in FIG. 14. As with the exampleof FIG. 13, there are a number of columns that extend through the stack.One column is referred to in the stack with reference numeral 656. Thecolumns contain memory cells. For example, each column may contain aNAND string. There are a number of bit lines (BL) above and below thestack.

Memory die 302 includes a substrate 640. On the top surface of substrate640 is circuitry 642, circuitry 644 and a plurality of sense amplifiers350 (FIG. 14 only depicts one sense amplifier) that together form acontrol circuit. In some embodiments, sense amplifiers 350, and/or othercircuitry 642/644 comprise CMOS electrical circuits. Memory structure326 is positioned directly above circuitry 642, circuitry 644 and aplurality of sense amplifiers 350. Memory structure 326 includes bitlines 650 above the memory structure and bit lines 652 below the memorystructure. Each sense amplifier 350 on substrate 640 is connected to abit line 652 below the stack. Each of the memory holes (NAND strings),such as memory hole 656 is connected to one of bit lines 650 or 652, asdescribed above.

Control die 304 includes a substrate 602. On the top surface ofsubstrate 602 is a control circuit comprising a plurality of senseamplifiers 350 (only one sense amplifier is depicted in FIG. 14),circuitry 664, circuitry 666, circuitry 668 and a plurality of word linedrivers 502 (only one word line driver is depicted in FIG. 14). In someembodiments, sense amplifiers 350, word line driver(s) 502, and/or othercircuitry 664/666/668 comprise CMOS electrical circuits. A senseamplifier 350 is connected to one of the bit lines 650 on top of thememory structure 326 by way of conductive pathway 624, TSV 622, bond pad576 b, bond pad 572 b, and conductive pathway 630. A word line driver502 is connected to one of the word lines (WL) 632 lines by way ofconductive pathway 616, TSV 618, bond pad 576 a, bond pad 572 a, andconductive pathway 508.

There is an external signal path that allows circuitry on the controldie 304 to communicate with an entity external to the integrated memoryassembly 130, such as memory controller 120. Therefore, circuitry 668 onthe control die 304 communicates with and provides an interface tomemory controller 120. Optionally, circuitry 668 on the control die 304may communicate with host 120. The external signal path includes via 670in control die 304 and bond pad 672.

FIG. 15 depicts one embodiment of a floor plan 704 for control die 304and FIG. 16 depicts one embodiment of a floor plan 702 for memory die302. Floor plan 704 shows one embodiment of the placement of some of thecomponents that comprise the control circuit on control die 304. Forexample, floor plan 704 shows placement of eight modules labeled SA/DL,which corresponds to sense amplifiers and data latches. Floor plan 704also includes eight modules labeled HVP (high voltage pumps),Input/Output circuits (I/O), row decoders (RD) and other logic toimplement various control functions (logic). In one embodiment, each ofthe components of floor plan 704 are electrical circuits positioned onthe surface of the substrate of control die 304. In other embodiments,floor plan 704 can place the depicted components in other locations,include other components, and/or include less than all of the componentsdepicted in FIG. 15.

Floor plan 702 shows one embodiment of the placement of some of thecomponents that comprise the control circuit on memory die 302. Forexample, floor plan 702 shows placement of eight modules labeled SA/DL,which corresponds to sense amplifiers and data latches. The remainder ofthe floor plan 702 is used for logic to implement various controlfunctions (logic). In one embodiment, each of the components of floorplan 702 are electrical circuits positioned on the surface of thesubstrate of memory die 302, and are positioned below memory structure326 so that the components of floor plan 702 are between the substrateand the memory structure. In other embodiments, floor plan 702 can placethe depicted components in other locations, include other components,and/or include less than all of the components depicted in FIG. 16. Inone embodiment, the logic to implement various control functions (logic)can be used to implement some of the functions depicted to be part ofcontrol die 304 in FIG. 2.

FIG. 17 depicts another embodiment of a floor plan 714 for control die304 and FIG. 18 depicts another embodiment of a floor plan 712 formemory die 302. Floor plan 714 shows one embodiment of the placement ofsome of the components that comprise the control circuit on control die304. For example, floor plan 714 shows placement of eight moduleslabeled SA/DL, which corresponds to sense amplifiers and data latches.Floor plan 714 also includes logic to implement various controlfunctions (logic) and Input/Output circuits (I/O). In one embodiment,each of the components of floor plan 714 are electrical circuitspositioned on the surface of the substrate of control die 304. In otherembodiments, floor plan 704 can place the depicted components in otherlocations, include other components, and/or include less than all of thecomponents depicted in FIG. 17.

Floor plan 712 shows another embodiment of the placement of some of thecomponents that comprise the control circuit on memory die 302. Forexample, floor plan 712 shows placement of eight modules labeled SA/DL,which corresponds to sense amplifiers and data latches. Floor plan 712also includes eight modules labeled HVP (high voltage pumps), rowdecoders (RD) and other logic to implement various control functions(logic). In one embodiment, each of the components of floor plan 712 areelectrical circuits positioned on the surface of the substrate of memorydie 302, and are positioned below memory structure 326 so that thecomponents of floor plan 712 are between the substrate and the memorystructure. In other embodiments, floor plan 712 can place the depictedcomponents in other locations, include other components, and/or includeless than all of the components depicted in FIG. 18.

In some embodiments, there may be more than one control die 304 and morethan one memory die 302 in an integrated memory assembly 130. In someembodiments, the integrated memory assembly 130 includes a stack ofmultiple control die 304 and multiple memory die 302. FIG. 19 depicts aside view of an embodiment of an integrated memory assembly 130 stackedon a substrate 802. The integrated memory assembly 130 has three controldie 304 and three memory die 302. Each control die 304 is directlybonded to one of the memory die 302. Some of the bond pads 8730, 824,are depicted. There may be many more bond pads. A space between two dies302, 304 that are bonded together is filled with a solid layer 848,which may be formed from epoxy or other resin or polymer. This solidlayer 848 protects the electrical connections between the dies 302, 304,and further secures the dies together. Various materials may be used assolid layer 848, but in embodiments, it may be Hysol epoxy resin fromHenkel Corp.

The integrated memory assembly 130 may for example be stacked with astepped offset, leaving the bond pads 804 at each level uncovered andaccessible from above. Wire bonds 806 connected to the bond pads 804connect the control die 304 to the substrate 802. A number of such wirebonds may be formed across the width of each control die 304 (i.e., intothe page of FIG. 8A).

A through silicon via (TSV) 812 may be used to route signals through acontrol die 304. A through silicon via (TSV) 814 may be used to routesignals through a memory die 302. The TSVs 812, 814 may be formedbefore, during or after formation of the integrated circuits in thesemiconductor dies 302, 304. The TSVs may be formed by etching holesthrough the wafers. The holes may then be lined with a barrier againstmetal diffusion. The barrier layer may in turn be lined with a seedlayer, and the seed layer may be plated with an electrical conductorsuch as copper, although other suitable materials such as aluminum, tin,nickel, gold, doped polysilicon, and alloys or combinations thereof maybe used.

Solder balls 808 may optionally be affixed to contact pads 810 on alower surface of substrate 802. The solder balls 808 may be used toelectrically and mechanically couple the integrated memory assembly 130to a host device such as a printed circuit board. Solder balls 808 maybe omitted where the integrated memory assembly 130 is to be used as anLGA package. The solder balls 808 may form a part of the interfacebetween the integrated memory assembly 130 and memory controller 102.

In the embodiment of FIG. 19, the memory dies 302 and the control dies304 are arranged as pairs. That is, each memory die 302 is bonded to andin communication with a corresponding/matching/paired control die.

FIG. 20 is a block diagram of a memory structure 900 that includes fourplanes 902, 904, 906 and 908, and does not utilize the technologyproposed herein. That is, memory structure 900 is used in a memorysystem that does not include sense amplifiers on both the memory die andthe control die. Therefore, only one sub-block per plane can be selectedfor a memory operation at a given time. FIG. 20 shows shading for thesub-blocks such that the horizontal shading represents unselectedsub-blocks and the crisscross shading represents selected sub-blocks.FIG. 20 show four sub-bocks of a same block for each plane 902, 904, 906and 908. For example, sub-blocks 902-0, 902-1, 902-2 and 902-3 aredepicted for a same block in plane 902. Of sub-blocks 902-0, 902-1,902-2 and 902-3, only sub-block 902-3 is selected for a memoryoperation, with the other sub-blocks being unselected (e.g., idle)during the memory operation. Sub-blocks 904-0, 904-1, 904-2 and 904-3are depicted for a same block in plane 904. Of sub-blocks 904-0, 904-1,904-2 and 902-3, only sub-block 904-3 is selected for a memoryoperation, with the other sub-blocks being unselected (e.g., idle)during the memory operation. Sub-blocks 906-0, 906-1, 906-2 and 906-3are depicted for a same block in plane 906. Of sub-blocks 906-0, 906-1,906-2 and 906-3, only sub-block 906-3 is selected for a memoryoperation, with the other sub-blocks being unselected (e.g., idle)during the memory operation. Sub-blocks 908-0, 908-1, 908-2 and 908-3are depicted for a same block in plane 908. Of sub-blocks 908-0, 908-1,908-2 and 908-3, only sub-block 908-3 is selected for a memoryoperation, with the other sub-blocks being unselected (e.g., idle)during the memory operation.

FIG. 21 is a block diagram of a memory structure 920 that includes fourplanes of memory cells 922, 924, 9026 and 928 that utilize/incorporatethe technology proposed herein. That is, memory structure 920 is used ina memory system that includes sense amplifiers on the memory die andsense amplifiers on the control die, as discussed above with respect toFIGS. 1-19. Therefore, two sub-blocks per plane can be selected forconcurrently performing a memory operation, which is twice as much asthe system of FIG. 20. FIG. 21 show four sub-bocks of a same block foreach plane 922, 924, 926 and 928. For example, sub-blocks 922-0, 922-1,922-2 and 922-3 are depicted for a same block in plane 922. Ofsub-blocks 922-0, 922-1, 922-2 and 922-3, sub-blocks 922-1 and 922-3 areselected for concurrently performing a memory operation, with the othersub-blocks being unselected (e.g., idle) during the memory operation.Sub-blocks 924-0, 924-1, 924-2 and 924-3 are depicted for a same blockin plane 924. Of sub-blocks 924-0, 924-1, 924-2 and 922-3, sub-blocks924-1 and 924-3 are selected for concurrently performing a memoryoperation, with the other sub-blocks being unselected (e.g., idle)during the memory operation. Sub-blocks 926-0, 926-1, 926-2 and 926-3are depicted for a same block in plane 926. Of sub-blocks 926-0, 926-1,926-2 and 926-3, sub-blocks 926-1 and 926-3 are selected forconcurrently performing a memory operation, with the other sub-blocksbeing unselected (e.g., idle) during the memory operation. Sub-blocks928-0, 928-1, 928-2 and 928-3 are depicted for a same block in plane928. Of sub-blocks 928-0, 928-1, 928-2 and 928-3, sub-blocks 908-1 and908-3 are selected for concurrently performing a memory operation, withthe other sub-blocks being unselected (e.g., idle) during the memoryoperation. Therefore, it can be see that using the technology describedherein provides a performance enhancement as twice as many memory cellscan be concurrently written to and/or read from. Note that when twosub-blocks of a same block are selected for concurrent writing or read,it is the memory cells of the two selected sub-blocks that are connectedto the same word line that are concurrently written to and/or read from.

FIG. 21 shows that a memory system with four planes can concurrentlywrite to and/or read from memory cells in eight sub-blocks (two in eachplane). Similarly, a memory system with eight planes can concurrentlywrite to and/or read from memory cells in sixteen sub-blocks (two ineach plane).

As discussed above, FIG. 6 depicts a top view of a portion of one blockfrom memory structure 326 according to the embodiment of FIG. 9(sub-blocks SB0 and SB1 are connected to bit lines above memorystructure 326 and sub-blocks SB2 and SB3 are connected to bit linesbelow memory structure 326). FIG. 22 depicts the same top view of thesame portion of the same one block from memory structure 326 accordingto the embodiment of FIG. 12 (sub-blocks SB0 and SB2 are connected tobit lines above memory structure 326 and sub-blocks SB1 and SB3 areconnected to bit lines below memory structure 326). In this embodimentof FIGS. 12 and 22, partial slits 404 and 408 can be removed. Partialslit 404 is used so that sub-block SB0 can be selected separately fromsub-block SB1. However, since SB0 is connected to bit lines above memorystructure 326 and SB1 is connected to bit lines below memory structure326, partial slit 404 is optional. Similarly, partial slit 408 is usedso that sub-block SB2 can be selected separately from sub-block SB3.However, since SB2 is connected to bit lines above memory structure 326and SB3 is connected to bit lines below memory structure 326 k partialslit 408 is optional. FIG. 23 depicts the same top view of the sameportion of the same one block as FIG. 22; however, partial slits 404 and408 have been removed. Removal of partial slits 404 and 408 allows theblock of memory cells to be smaller, as width W23 of FIG. 23 is smallerthan width W22 of FIG. 22. This can result in a smaller die size, whichsaves costs and space.

FIG. 24 is a flow chart describing one embodiment of a process forperforming a memory operation using the structures discussed above inFIGS. 1-23. In step 1002 of FIG. 24, a request to perform a memoryoperation (e.g., write or read) is received at integrated memoryassembly 130. For example, the request is received at control die 304.The request can be from a memory controller, a host, or anotherintegrated assembly. In step 1004, the integrated memory assembly 130performs the memory operation on a first portion of a first block of thenon-volatile memory cells using a first plurality of sense amplifiers.For example, the control circuit (including sense amplifiers) residingon memory die 302 is used to perform the memory operation in step 1004.The control circuit of control die 304 can (in some embodiments) also beused to perform the memory operations. For example, the memory operationmay be performed at the direction of the state machine on control die304, using the sense amplifiers of the memory die connected to a firstsub-block of a selected block of memory cells on the memory die 302. Instep 1006, the integrated memory assembly 130 concurrently performs thememory operation on a second portion of the first block of thenon-volatile memory cells using a second plurality of sense amplifiers.For example, the control circuit (including sense amplifiers) residingon control die 304 is used to perform the memory operation. In oneembodiment, steps 1004 and 1006 are performed concurrently, as discussedabove. The process of FIG. 24 can be used with any of the embodimentsdiscussed above. More details of the steps of FIG. 24 are provided belowwith respect to FIGS. 25-29.

FIG. 25 is a flow chart describing one embodiment of a process forperforming a write operation. The process of FIG. 25 is one exampleimplementation of the process of FIG. 24. In step 1102 of FIG. 25,integrated memory assembly 130 receives a request to perform a writeoperation at the integrated memory assembly. For example, control die304 may receive (from a memory controller) a write command, host datafor the write command and one or more write addresses in the memorystructure to write the host data to. The host data is data received fromthe host. In one embodiment, the memory controller received the hostdata from the host and forwards it to the integrated memory assembly. Instep 1104, control die 304 applies a program voltage signal on aselected word line of memory structure 326. Additionally, the selectionlines (Top_SGL and Bottom_SGL) are biases as depicted in FIG. 12A or 12B(or another suitable biasing scheme). In step 1106, a first plurality ofsense amplifiers on memory die 302 provide programming conditions on thefirst plurality of bit lines while the program voltage is driven on theselected word line. The first plurality of sense amplifiers on memorydie 302 are connected to bit lines under memory structure 326, asdiscussed above. In step 1108, the second plurality of sense amplifierson control die 304 provide programming conditions on the secondplurality of bit lines while the program voltage is driven on theselected word line. The second plurality of sense amplifiers on controldie 304 are connected to bit lines above memory structure 326, asdiscussed above. In one embodiment, the sense amplifiers provideprogramming conditions by apply a small voltage or 0 volts on the bitlines. As a result of steps 1102-1108, host data is programmed intomemory structure 326. In one embodiment, step 1106 is performedconcurrently with step 1108 so that memory cells connected to a commonword line but in two sub-blocks are written to concurrently.

At the end of a successful programming process, the threshold voltagesof the memory cells should be within one or more distributions ofthreshold voltages for programmed memory cells or within a distributionof threshold voltages for erased memory cells, as appropriate. FIG. 26is a graph of threshold voltage versus number of memory cells, andillustrates example threshold voltage distributions for memory structure326 when each memory cell stores three bits of data. Other embodiments,however, may use other data capacities per memory cell (e.g., such asone, two, four, or five bits of data per memory cell). FIG. 26 showseight threshold voltage distributions, corresponding to eight datastates. For a data state N, that data state N has higher thresholdvoltages than data state N−1 and lower threshold voltages than datastate N+1. The first threshold voltage distribution (data state) S0represents memory cells that are erased. The other seven thresholdvoltage distributions (data states) S1-S7 represent memory cells thatare programmed and, therefore, are also called programmed states orprogrammed data states. In some embodiments, data states S1-S7 canoverlap, with controller 122 relying on error correction to identify thecorrect data being stored.

FIG. 26 shows seven read reference voltages, Vr1, Vr2, Vr3, Vr4, Vr5,Vr6, and Vr7 for reading data from memory cells. By testing (e.g.,performing sense operations) whether the threshold voltage of a givenmemory cell is above or below the seven read reference voltages, thesystem can determine what data state (i.e., S0, S1, S2, S3, . . . ) amemory cell is in.

FIG. 26 also shows seven verify reference voltages, Vv1, Vv2, Vv3, Vv4,Vv5, Vv6, and Vv7 (also referred to as verify target voltages). Whenprogramming memory cells to data state S1, the system will test whetherthose memory cells have a threshold voltage greater than or equal toVv1. When programming memory cells to data state S2, the system willtest whether the memory cells have threshold voltages greater than orequal to Vv2. When programming memory cells to data state S3, the systemwill determine whether memory cells have their threshold voltage greaterthan or equal to Vv3. When programming memory cells to data state S4,the system will test whether those memory cells have a threshold voltagegreater than or equal to Vv4. When programming memory cells to datastate S5, the system will test whether those memory cells have athreshold voltage greater than or equal to Vv5. When programming memorycells to data state S6, the system will test whether those memory cellshave a threshold voltage greater than or equal to Vv6. When programmingmemory cells to data state S7, the system will test whether those memorycells have a threshold voltage greater than or equal to Vv7.

In one embodiment, known as full sequence programming, memory cells canbe programmed from the erased data state S0 directly to any of theprogrammed data states S1-S7. For example, a population of memory cellsto be programmed (e.g., memory cells that are in two sub-blocks of aplane and connected to a same word line) may first be erased so that allmemory cells in the population are in erased data state S0. Then, aprogramming process is used to program memory cells directly into datastates S1, S2, S3, S4, S5, S6, and/or S7. For example, while some memorycells are being programmed from data state S0 to data state S1, othermemory cells are being programmed from data state S0 to data state S2and/or from data state S0 to data state S3, and so on. The arrows ofFIG. 26 represent the full sequence programming. The technologydescribed herein can also be used with other types of programming inaddition to full sequence programming, including (but not limited to)multiple stage/phase programming.

Each threshold voltage distribution (data state) of FIG. 26 correspondsto predetermined values for the set of data bits stored in the memorycells. The specific relationship between the data programmed into thememory cell and the threshold voltage levels of the memory cell dependsupon the data encoding scheme adopted for the memory cells. In oneembodiment, data values are assigned to the threshold voltage rangesusing a Gray code assignment so that if the threshold voltage of amemory erroneously shifts to its neighboring physical state, only onebit will be affected.

FIG. 27 is a table describing one example of an assignment of datavalues to data states. In the table of FIG. 27, S0=111 (erased state),S1=110, S2=100, S3=000, S4=010, S5=011, S6=001 and S7=101. Otherencodings of data can also be used. No particular data encoding isrequired by the technology disclosed herein. In one embodiment, when ablock is subjected to an erase operation, all memory cells are moved todata state S0, the erased state.

In general, during verify operations and read operations, the selectedword line is connected to a voltage (one example of a reference signal),a level of which is specified for each read operation (e.g., see readreference voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7, of FIG. 26) orverify operation (e.g. see verify reference voltages Ev, Vv1, Vv2, Vv3,Vv4, Vv5, Vv6, and Vv7 of FIG. 26) in order to determine whether athreshold voltage of the concerned memory cell has reached such level.After applying the word line voltage, the conduction current of thememory cell is measured to determine whether the memory cell turned on(conducted current) in response to the voltage applied to the word line.If the conduction current is measured to be greater than a certainvalue, then it is assumed that the memory cell turned on and the voltageapplied to the word line is greater than the threshold voltage of thememory cell. If the conduction current is not measured to be greaterthan the certain value, then it is assumed that the memory cell did notturn on and the voltage applied to the word line is not greater than thethreshold voltage of the memory cell. During a read or verify process,the unselected memory cells are provided with one or more read passvoltages (also referred to as bypass voltages) at their control gates sothat these memory cells will operate as pass gates (e.g., conductingcurrent regardless of whether they are programmed or erased).

There are many ways to measure the conduction current of a memory cellduring a read or verify operation. In one example, the conductioncurrent of a memory cell is measured by the rate it discharges orcharges a dedicated capacitor in the sense amplifier. In anotherexample, the conduction current of the selected memory cell allows (orfails to allow) the NAND string that includes the memory cell todischarge a corresponding bit line. The voltage on the bit line ismeasured after a period of time to see whether it has been discharged ornot. Note that the technology described herein can be used withdifferent methods known in the art for verifying/reading. Other read andverify techniques known in the art can also be used.

FIG. 28 is a flowchart describing one embodiment of a process forprogramming memory structure 326. In one example embodiment, the processof FIG. 28 is performed on control die 302 using the sense amplifiers onthe control die and the sense amplifiers on the memory die as discussedabove, at the direction of state machine 312. The process of FIG. 28 isperformed to implement the full sequence programming of FIG. 26, as wellas other programming schemes including multi-stage programming. Whenimplementing multi-stage programming, the process of FIG. 28 is used toimplement any/each stage of the multi-stage programming process. Theprocess of FIG. 28 can be used to perform the process of FIG. 25.

Typically, the program voltage applied to the control gates (via aselected word line) during a program operation is applied as a series ofprogram pulses (voltage pulses). Between programming pulses are a set ofverify pulses to perform verification. In many implementations, themagnitude of the program pulses is increased with each successive pulseby a predetermined step size. In step 1202 of FIG. 28, the programmingvoltage (Vpgm) is initialized to the starting magnitude (e.g., ˜12-16Vor another suitable level) and a program counter PC maintained by statemachine 312 is initialized at 1. In step 1204, a program pulse of theprogram signal Vpgm is applied to the selected word line (the word lineselected for programming). In one embodiment, the group of memory cellsbeing programmed concurrently are all connected to the same word line(the selected word line). The unselected word lines receive one or moreboosting voltages (e.g., ˜7-11 volts) to perform boosting schemes knownin the art. The program pulse applied to the selected word line is anexample of the program voltage signal of step 1104 of FIG. 25. In oneembodiment, if a memory cell should be programmed, then thecorresponding bit line is grounded (e.g., the programming condition ofsteps 1106 and 1108 of FIG. 25). On the other hand, if the memory cellshould remain at its current threshold voltage, then the correspondingbit line is connected to Vdd to inhibit programming. In step 1204, theprogram pulse is concurrently applied to all memory cells connected tothe selected word line so that all of the memory cells connected to theselected word line are programmed concurrently. That is, they areprogrammed at the same time or during overlapping times (both of whichare considered concurrent). In this manner all of the memory cellsconnected to the selected word line will concurrently have theirthreshold voltage change, unless they have been locked out fromprogramming.

In step 1206, the appropriate memory cells are verified using theappropriate set of verify reference voltages to perform one or moreverify operations. In one embodiment, the verification process isperformed by testing whether the threshold voltages of the memory cellsselected for programming have reached the appropriate verify referencevoltage. In step 1208, it is determined whether all the memory cellshave reached their target threshold voltages (pass). If so, theprogramming process is complete and successful because all selectedmemory cells were programmed and verified to their target states. Astatus of “PASS” (or success) is reported in step 1210. If, in step1208, it is determined that not all of the memory cells have reachedtheir target threshold voltages (fail), then the programming processcontinues to step 1212. In step 1212, the system counts the number ofmemory cells that have not yet reached their respective target thresholdvoltage distribution. That is, the system counts the number of memorycells that have, so far, failed the verify process. This counting can bedone by the state machine 312, the controller 120, or other logic. Inone implementation, each of the sense blocks will store the status(pass/fail) of their respective memory cells. In one embodiment, thereis one total count, which reflects the total number of memory cellscurrently being programmed that have failed the last verify step. Inanother embodiment, separate counts are kept for each data state.

In step 1214, it is determined whether the count from step 1212 is lessthan or equal to a predetermined limit. In one embodiment, thepredetermined limit is a number of bits that can be corrected by errorcorrection codes (ECC) during a read process for the page of memorycells. If the number of failed cells is less than or equal to thepredetermined limit, than the programming process can stop and a statusof “PASS” is reported in step 1210. In this situation, enough memorycells programmed correctly such that the few remaining memory cells thathave not been completely programmed can be corrected using ECC duringthe read process. In some embodiments, step 1212 will count the numberof failed cells for each sector, each target data state or other unit,and those counts will individually or collectively be compared to one ormore thresholds in step 1214.

In one embodiment, the predetermined limit can be less than the totalnumber of bits that can be corrected by ECC during a read process toallow for future errors. When programming less than all of the memorycells for a page, or comparing a count for only one data state (or lessthan all states), than the predetermined limit can be a portion(pro-rata or not pro-rata) of the number of bits that can be correctedby ECC during a read process for the page of memory cells. In someembodiments, the limit is not predetermined. Instead, it changes basedon the number of errors already counted for the page, the number ofprogram-erase cycles performed or other criteria.

If number of failed memory cells is not less than the predeterminedlimit, than the programming process continues at step 1216 and theprogram counter PC is checked against the program limit value (PL).Examples of program limit values include 6, 20 and 30; however, othervalues can be used. If the program counter PC is not less than theprogram limit value PL, then the program process is considered to havefailed and a status of FAIL is reported in step 1218. If the programcounter PC is less than the program limit value PL, then the processcontinues at step 1220 during which time the Program Counter PC isincremented by 1 and the program voltage Vpgm is stepped up to the nextmagnitude. For example, the next pulse will have a magnitude greaterthan the previous pulse by a step size (e.g., a step size of 0.1-0.8volts). After step 1220, the process loops back to step 1204 and anotherprogram pulse is applied to the selected word line so that anotheriteration (steps 1204-1220) of the programming process of FIG. 28 isperformed.

Because it is possible that errors can occur when programming orreading, and errors can occur while storing data (e.g., due to electronsdrifting, data retention issues or other phenomenon), error correctionis used with the programming of data. Memory systems often use ErrorCorrection Codes (ECC) to protect data from corruption. Many ECC codingschemes are well known in the art. These conventional error correctioncodes are especially useful in large scale memories, including flash(and other non-volatile) memories, because of the substantial impact onmanufacturing yield and device reliability that such coding schemes canprovide, rendering devices that have a few non-programmable or defectivecells as useable. Of course, a tradeoff exists between the yield savingsand the cost of providing additional memory cells to store the code bits(i.e., the code “rate”). As such, some ECC codes are better suited forflash memory devices than others. Generally, ECC codes for flash memorydevices tend to have higher code rates (i.e., a lower ratio of code bitsto data bits) than the codes used in data communications applications(which may have code rates as low as 1/2). Examples of well-known ECCcodes commonly used in connection with flash memory storage includeReed-Solomon codes, other BCH codes, Hamming codes, and the like.Sometimes, the error correction codes used in connection with flashmemory storage are “systematic,” in that the data portion of theeventual code word is unchanged from the actual data being encoded, withthe code or parity bits appended to the data bits to form the completecode word.

The particular parameters for a given error correction code include thetype of code, the size of the block of actual data from which the codeword is derived, and the overall length of the code word after encoding.For example, a typical BCH code applied to a sector of 512 bytes (4096bits) of data can correct up to four error bits, if at least 60 ECC orparity bits are used. Reed-Solomon codes are a subset of BCH codes, andare also commonly used for error correction. For example, a typicalReed-Solomon code can correct up to four errors in a 512 byte sector ofdata, using about 72 ECC bits. In the flash memory context, errorcorrection coding provides substantial improvement in manufacturingyield, as well as in the reliability of the flash memory over time.

In some embodiments, controller 120 receives host data (also referred toas user data or data from an entity external to the memory system), alsoreferred to as information bits, that is to be stored non-volatilememory structure 326. The informational bits are represented by thematrix i=[1 0] (note that two bits are used for example purposes only,and many embodiments have code words longer than two bits). An errorcorrection coding process (such as any of the processes mentioned aboveor below) is implemented by ECC engine 158 of controller 120 in whichparity bits are added to the informational bits to provide datarepresented by the matrix or code word v=[1 0 1 0], indicating that twoparity bits have been appended to the data bits. Other techniques can beused that map input data to output data in more complex manners. Forexample, low density parity check (LDPC) codes, also referred to asGallager codes, can be used. More details about LDPC codes can be foundin R. G. Gallager, “Low-density parity-check codes,” IRE Trans. Inform.Theory, vol. IT-8, pp. 21 28, January 1962; and D. MacKay, InformationTheory, Inference and Learning Algorithms, Cambridge University Press2003, chapter 47. In practice, such LDPC codes are typically applied(e.g., by ECC engine 158) to multiple pages encoded across a number ofstorage elements, but they do not need to be applied across multiplepages. In some embodiments, the ECC process (encoding data and/ordecoding data) can be performed by ECC engine 330 on control die 304. Insome embodiments, the ECC process (encoding data and/or decoding data)can be performed by an ECC engine on memory die 302 (e.g., the ECCengine is part of the logic depicted in FIG. 16.

In one embodiment, programming serves to raise the threshold voltage ofthe memory cells to one of the programmed data states S1-S7. Erasingserves to lower the threshold voltage of the memory cells to the Erasedata state S0.

One technique to erase memory cells in some memory devices is to bias ap-well (or other types of) substrate to a high voltage to charge up aNAND channel. An erase enable voltage (e.g., a low voltage) is appliedto control gates of memory cells while the NAND channel is at a highvoltage to erase the non-volatile storage elements (memory cells).Herein, this is referred to as p-well erase.

Another approach to erasing memory cells is to generate gate induceddrain leakage (GIDL) current to charge up the NAND string channel. Anerase enable voltage is applied to control gates of the memory cells,while maintaining the NAND string channel potential to erase the memorycells. Herein, this is referred to as GIDL erase. Both p-well erase andGIDL erase may be used to lower the threshold voltage (Vt) of memorycells.

In one embodiment, the GIDL current is generated by causing adrain-to-gate voltage at a select transistor (e.g., SGD and/or SGS). Atransistor drain-to-gate voltage that generates a GIDL current isreferred to herein as a GIDL voltage. The GIDL current may result whenthe select transistor drain voltage is significantly higher than theselect transistor control gate voltage. GIDL current is a result ofcarrier generation, i.e., electron-hole pair generation due toband-to-band tunneling and/or trap-assisted generation. In oneembodiment, GIDL current may result in one type of carriers, e.g.,holes, predominantly moving into NAND channel, thereby raising potentialof the channel. The other type of carriers, e.g., electrons, areextracted from the channel, in the direction of a bit line or in thedirection of a source line, by an electric field. During erase, theholes may tunnel from the channel to a charge storage region of memorycells and recombine with electrons there, to lower the threshold voltageof the memory cells.

The GIDL current may be generated at either end of the NAND string. Afirst GIDL voltage may be created between two terminals of a selecttransistor (e.g., drain side select transistor) that is connected to abit line to generate a first GIDL current. A second GIDL voltage may becreated between two terminals of a select transistor (e.g., source sideselect transistor) that is connected to a source line to generate asecond GIDL current. Erasing based on GIDL current at only one end ofthe NAND string is referred to as a one-sided GIDL erase. Erasing basedon GIDL current at both ends of the NAND string is referred to as atwo-sided GIDL erase.

FIG. 29 is a flow chart describing one embodiment of a process forperforming a read operation. The process of FIG. 29 is one exampleimplementation of the process of FIG. 24. In step 1302 of FIG. 29,integrated memory assembly 130 receives a request to perform a readoperation, including receiving one or more read addresses. For example,control die 302 may receive a read command and a read address from amemory controller. In step 1304, control die 304 applies one or moreread reference voltages. For example, the word line drivers discussedabove can be used by control die 304 to drive any of the read referencevoltages (e.g., Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and/or Vr7) on theselected word line. Additionally, the selection lines (Top_SGL andBottom_SGL) are biases as depicted in FIG. 12A or 12B (or anothersuitable biasing scheme). In step 1306, the first plurality of senseamplifiers on the memory die sense conditions of the first plurality ofmemory cells (e.g., first sub-block) via the first plurality of bitlines (e.g., bit lines below the memory structure) in response to theone or more read reference voltages on the selected word line. In step1308, the second plurality of sense amplifiers on the control die senseconditions of the second plurality of memory cells (e.g., secondsub-block of same bock as first sub-block) via the second plurality ofbit lines (e.g., bit lines below the memory structure) in response tothe one or more read reference voltages on the selected word line. Steps1306 and 1308 are performed concurrently so that two sub-blocks perplane are read at the same time.

FIG. 30 is a block diagram depicting further details of one embodimentof an integrated memory assembly that implements a three die system. Forexample, FIG. 30 depicts control die 304 bonded to memory die 302 asdescribed above with respect to FIG. 13, and also depicts an additionalcontrol die 1400 (third die) bonded (connected) to memory die 302. Inone embodiment, control die 1400 has the same structure as control die304, including a control circuit comprising a plurality of senseamplifiers 350. In some embodiments, control die 1400 has a plurality ofsense amplifiers 350 like control die 304, but control die 1400 does notinclude word line drivers and other logic that does not need to beduplicated in control die 1400 (as compared to control die 304).

Each sense amplifier 350 is connected to one bit line. Threerepresentative bit lines (BL1, BL2 and BL3) are depicted. Bit line BL3can be positioned below or above the memory cells. For example, FIG. 9shows half of the bit lines connected to the sense amplifiers on memorydie 302 and half of the bit lines connected to the sense amplifiers oncontrol die 304, while in embodiments of FIG. 30 zero or more of the bitlines below the memory array can be connected to sense amplifiers ofcontrol die 1400 and zero or more of the bit lines above the memoryarray can be connected to sense amplifiers of control die 1400. In thismanner, the sense amplifiers on memory die 302 are connected to a firstset of memory cells in a block, the sense amplifiers on control die 304are connected to a second set of memory cells in the same block, and thesense amplifiers on control die 1400 are connected to a third set ofmemory cells in the same block. In one example embodiment, the senseamplifiers on memory die 302 are connected to memory cells in a firstsub-block of a block, the sense amplifiers on control die 304 areconnected to memory cells in a second sub-block of the same block, andthe sense amplifiers on control die 1400 are connected to memory cellsin a third sub-block of the same block.

Memory die 302 further incudes bond pads 1402. Control die 1404 includesbond pads 1404 connected to bond pads 1402. There may be “n” bond pads1402 and “n” bond pads 1404 to transfer signals between the bit lines ofmemory die 302 and the sense amplifiers of control die 1404.

In the embodiment of FIG. 13, the control circuit of memory die 302performs a memory operation on a first subset of the memory cellsconcurrently with the control circuit of control die 304 performing thememory operation on a second subset of the memory cells. In theembodiment of FIG. 30, the control circuit of control die 1400 isconfigured to be used to perform the memory operation on a third subsetof the memory cells concurrently with the control circuit of memory die302 performing the memory operation on the first subset of the memorycells and the control circuit of control die 304 performing the memoryoperation on the second subset of the memory cells. Other embodimentsmay include additional control die (e.g., more than two control dieswith sense amplifiers connected to bit lines on the memory die).

A memory has been described that includes control circuits (e.g.,including sense amplifiers) on the same die as the memory array andcontrol circuits (e.g., including sense amplifiers) on a different diethan the memory array, so that the number of sense amplifiers (orequivalent circuits) can be increased. Increasing the number of senseamplifiers increases the amount of parallelism, which results in anincrease in performance of the memory system. Additionally, theincreases in the amount of parallelism can result in a more efficientuse of power and additional functionality.

One embodiment includes a non-volatile storage apparatus comprising afirst semiconductor die and a second semiconductor die. The firstsemiconductor die comprises a substrate, a first control circuitpositioned on the substrate, and non-volatile memory cells positioneddirectly above the first control circuit. The second semiconductor diecomprises a second control circuit on a substrate. The secondsemiconductor die further comprises an interface to a memory controllerand an interface to the first semiconductor die. The secondsemiconductor die is directly connected to the first semiconductor die.The first control circuit is configured to be used to perform a memoryoperation on a first subset of the non-volatile memory cells while thesecond control circuit is configured to be used to concurrently performa memory operation on a second subset of the non-volatile memory cells.

In one example implementation, the non-volatile memory cells areorganized into blocks of non-volatile memory cells; the first subset ofthe non-volatile memory cells and the second subset of the non-volatilememory cells are part of a first block and connected to a first wordline; the first block is divided into multiple sub-blocks including afirst sub-block and a second sub-block; the first subset of thenon-volatile memory cells are in the first sub-block; the second subsetof the non-volatile memory cells are in the second sub-block; the firstcontrol circuit comprises a first set of sense amplifiers that areconnected to the first subset of the non-volatile memory cells in thefirst sub-block; and the second control circuit comprises a second setof sense amplifiers that are connected to the second subset ofnon-volatile memory cells in the second sub-block.

One example implementation further comprises a third semiconductor diecomprising a third control circuit, the third semiconductor die isconnected to the first semiconductor die, the third control circuit isconfigured to be used to perform the memory operation on a third subsetof the non-volatile memory cells concurrently with the first controlcircuit performing the memory operation on the first subset of thenon-volatile memory cells and the second control circuit performing thememory operation on the second subset of the non-volatile memory cells.

One embodiment includes a non-volatile storage apparatus comprising amemory controller and an integrated memory assembly separate from thememory controller and in communication with the memory controller via acommunication path. The integrated memory assembly comprises a memorydie and a control die bonded to the memory die. The memory die comprisesa three dimensional non-volatile memory structure and a first pluralityof sense amplifiers. The first plurality of sense amplifiers areconnected to the memory structure and are positioned on a substrate ofthe memory die between the memory structure and the substrate such thatthe memory structure is directly above the first plurality of senseamplifiers. The control die has a first interface for communicating withthe memory controller and a second interface for communicating with thememory die. The second interface is wider than the first interface. Thecontrol die comprises a second plurality of sense amplifiers that areconnected to the memory structure via the second interface. The firstplurality of sense amplifiers and the second plurality of senseamplifiers are configured to be used to concurrently write data to thememory structure.

In one example implementation, the first plurality of sense amplifiersand the second plurality of sense amplifiers are configured to be usedto read data from the memory structure such that the first plurality ofsense amplifiers are used to read data from a first portion of thememory structure while the second plurality of sense amplifiers are usedto concurrently read data from a second portion of the memory structure.

One embodiment includes a method of operating a non-volatile storageapparatus, comprising: receiving a request to perform a memory operationat an integrated memory assembly, the integrated memory assemblycomprises a memory die and a control die bonded to the memory die, thememory die comprises a three dimensional non-volatile memory structureand a first plurality of sense amplifiers, the control die comprises asecond plurality of sense amplifiers that are connected to the memorystructure, the memory structure is organized into blocks of non-volatilememory cells; and performing the memory operation on a first portion ofa first block of the non-volatile memory cells using the first pluralityof sense amplifiers while concurrently performing the memory operationon a second portion of the first block of the non-volatile memory cellsusing the second plurality of sense amplifiers.

For purposes of this document, reference in the specification to “anembodiment,” “one embodiment,” “some embodiments,” or “anotherembodiment” may be used to describe different embodiments or the sameembodiment.

For purposes of this document, a connection may be a direct connectionor an indirect connection (e.g., via one or more others parts). In somecases, when an element is referred to as being connected or coupled toanother element, the element may be directly connected to the otherelement or indirectly connected to the other element via one or moreintervening elements. When an element is referred to as being directlyconnected to another element, then there are no intervening elementsbetween the element and the other element. Two devices are “incommunication” if they are directly or indirectly connected so that theycan communicate electronic signals between them.

For purposes of this document, the term “based on” may be read as “basedat least in part on.”

For purposes of this document, without additional context, use ofnumerical terms such as a “first” object, a “second” object, and a“third” object may not imply an ordering of objects, but may instead beused for identification purposes to identify different objects.

For purposes of this document, the term “set” of objects may refer to a“set” of one or more of the objects.

The foregoing detailed description has been presented for purposes ofillustration and description. It is not intended to be exhaustive or tolimit to the precise form disclosed. Many modifications and variationsare possible in light of the above teaching. The described embodimentswere chosen in order to best explain the principles of the proposedtechnology and its practical application, to thereby enable othersskilled in the art to best utilize it in various embodiments and withvarious modifications as are suited to the particular use contemplated.It is intended that the scope be defined by the claims appended hereto.

What is claimed is:
 1. A non-volatile storage apparatus, comprising: afirst semiconductor die comprising a substrate, a first control circuitpositioned on the substrate, and non-volatile memory cells positioneddirectly above the first control circuit; and a second semiconductor diecomprising a second control circuit, the second semiconductor diefurther comprises an interface to a memory controller and an interfaceto the first semiconductor die, the second semiconductor die is directlyconnected to the first semiconductor die, the first control circuit isconfigured to be used to perform a memory operation on a first subset ofthe non-volatile memory cells, the second control circuit is configuredto be used to perform the memory operation on a second subset of thenon-volatile memory cells.
 2. The non-volatile storage apparatus ofclaim 1, wherein: the first control circuit is configured to perform thememory operation on the first subset of the non-volatile memory cellswhile the second control circuit concurrently performs the memoryoperation on the second subset of the non-volatile memory cells.
 3. Thenon-volatile storage apparatus of claim 1, wherein: the first controlcircuit comprises a first set of sense amplifiers that are connected tothe first subset of the non-volatile memory cells; the second controlcircuit comprises a second set of sense amplifiers that are connected tothe second subset of non-volatile memory cells; and the first set ofsense amplifiers are configured to be used to perform the memoryoperation on the first subset of the non-volatile memory cells while thesecond set of sense amplifiers are used to concurrently perform thememory operation on the second subset of the non-volatile memory cells.4. The non-volatile storage apparatus of claim 3, wherein: thenon-volatile memory cells are organized into blocks of non-volatilememory cells; the first subset of the non-volatile memory cells and thesecond subset of the non-volatile memory cells are part of a same blockand connected to a same word line.
 5. The non-volatile storage apparatusof claim 4, further comprising: a first plurality of bit lines below thenon-volatile memory cells, the first plurality of bit lines areconnected to the first set of sense amplifiers and the first subset ofthe non-volatile memory cells; and a second plurality of bit lines abovethe non-volatile memory cells, the second plurality of bit lines areconnected to the second set of sense amplifiers and the second subset ofthe non-volatile memory cells.
 6. The non-volatile storage apparatus ofclaim 5, wherein the first semiconductor die comprising furthercomprises: a first source line above the non-volatile memory cells, thefirst source line is connected to the first subset of non-volatilememory cells; and a second source line below the non-volatile memorycells, the second source line is connected to the second subset ofnon-volatile memory cells.
 7. The non-volatile storage apparatus ofclaim 6, wherein: the first source line is continuous across the sameblock.
 8. The non-volatile storage apparatus of claim 6, wherein: thefirst source line is divided into non-continuous sections.
 9. Thenon-volatile storage apparatus of claim 1, wherein: the non-volatilememory cells are part of vertical NAND strings that each include a firstselect gate at a first end and a second select gate at a second end; thefirst select gates of the NAND strings are connected by a first selectline that operates as a source side select line for a first subset ofthe NAND strings and a drain side select line for a second subset of theNAND strings; and the second select gates of the NAND strings areconnected by a second select line that operates as a drain side selectline for the first subset of the NAND strings and a source side selectline for the second subset of the NAND strings.
 10. The non-volatilestorage apparatus of claim 1, wherein: the non-volatile memory cells areorganized into blocks of non-volatile memory cells; the first subset ofthe non-volatile memory cells and the second subset of the non-volatilememory cells are part of a first block and connected to a first wordline; the first block is divided into multiple sub-blocks including afirst sub-block and a second sub-block; the first subset of thenon-volatile memory cells are in the first sub-block; the second subsetof the non-volatile memory cells are in the second sub-block; the firstcontrol circuit comprises a first set of sense amplifiers that areconnected to the first subset of the non-volatile memory cells in thefirst sub-block; and the second control circuit comprises a second setof sense amplifiers that are connected to the second subset ofnon-volatile memory cells in the second sub-block
 11. The non-volatilestorage apparatus of claim 10, wherein: a third subset of thenon-volatile memory cells are connected to the first word line and arein a third sub-block of the first block; a fourth subset of thenon-volatile memory cells are connected to the first word line and arein a fourth sub-block of the first block; the first control circuit isconnected to the third subset of the non-volatile memory cells; thesecond control circuit is connected to the fourth subset of thenon-volatile memory cells; the first control circuit is configured toperform the memory operation on the third subset of the non-volatilememory cells while the second control circuit concurrently performs thememory operation on the fourth subset of the non-volatile memory cells.12. The non-volatile storage apparatus of claim 1, further comprising: athird semiconductor die comprising a third control circuit, the thirdsemiconductor die is connected to the first semiconductor die, the thirdcontrol circuit is configured to be used to perform the memory operationon a third subset of the non-volatile memory cells concurrently with thefirst control circuit performing the memory operation on the firstsubset of the non-volatile memory cells and the second control circuitperforming the memory operation on the second subset of the non-volatilememory cells.
 13. A non-volatile storage apparatus, comprising: a memorycontroller; and an integrated memory assembly separate from the memorycontroller and in communication with the memory controller via acommunication path, the integrated memory assembly comprises a memorydie and a control die bonded to the memory die, the memory die comprisesa three dimensional non-volatile memory structure and a first pluralityof sense amplifiers, the first plurality of sense amplifiers areconnected to the memory structure and are positioned on a substrate ofthe memory die between the memory structure and the substrate such thatthe memory structure is directly above the first plurality of senseamplifiers, the control die has a first interface for communicating withthe memory controller and a second interface for communicating with thememory die, the second interface is wider than the first interface, thecontrol die comprises a second plurality of sense amplifiers that areconnected to the memory structure via the second interface, the firstplurality of sense amplifiers and the second plurality of senseamplifiers are configured to be used to write data to the memorystructure.
 14. The non-volatile storage apparatus of claim 13, whereinthe first plurality of sense amplifiers and the second plurality ofsense amplifiers are configured to be used to write data to the memorystructure such that the first plurality of sense amplifiers are used towrite data to a first portion of the memory structure while the secondplurality of sense amplifiers are used to concurrently write data to asecond portion of the memory structure.
 15. The non-volatile storageapparatus of claim 13, wherein: the first plurality of sense amplifiersand the second plurality of sense amplifiers are configured to be usedto read data from the memory structure such that the first plurality ofsense amplifiers are used to read data from a first portion of thememory structure while the second plurality of sense amplifiers are usedto concurrently read data from a second portion of the memory structure.16. The non-volatile storage apparatus of claim 13, wherein: the memorystructure is organized into blocks of non-volatile memory cells; and thefirst plurality of sense amplifiers and the second plurality of senseamplifiers are configured to be used to write data to the memorystructure such that the first plurality of sense amplifiers are used towrite data to memory cells of a first subset of memory cells of a blockof memory cells while the second plurality of sense amplifiers are usedto concurrently write data to a second subset of memory cells of theblock of memory cells, the first subset of memory cells and the secondsubset of memory cells are connected to a selected word line.
 17. Amethod of operating a non-volatile storage apparatus, comprising:receiving a request to perform a memory operation at an integratedmemory assembly, the integrated memory assembly comprises a memory dieand a control die bonded to the memory die, the memory die comprises athree dimensional non-volatile memory structure and a first plurality ofsense amplifiers, the control die comprises a second plurality of senseamplifiers that are connected to the memory structure, the memorystructure is organized into blocks of non-volatile memory cells; andperforming the memory operation on a first portion of a first block ofthe non-volatile memory cells using the first plurality of senseamplifiers while concurrently performing the memory operation on asecond portion of the first block of the non-volatile memory cells usingthe second plurality of sense amplifiers.
 18. The method of claim 17,wherein: the first portion of the first block of the non-volatile memorycells comprises a first plurality of memory cells connected to aselected word line, a first source line above the memory structure and afirst plurality of bit lines below the memory structure; the firstplurality of bit lines are connected to the first plurality of senseamplifiers; the second portion of the first block of the non-volatilememory cells comprises a second plurality of memory cells connected tothe selected word line, a second source line below the memory structureand a second plurality of bit lines above the memory structure; and thesecond plurality of bit lines are connected to the second plurality ofsense amplifiers.
 19. The method of 18, wherein: the performing thememory operation on the first portion of the first block of thenon-volatile memory cells using the first plurality of sense amplifierscomprises the first plurality of sense amplifiers on the memory diesensing conditions of the first plurality of memory cells via the firstplurality of bit lines in response to a read reference voltage on theselected word line; and the performing the memory operation on thesecond portion of the first block of the non-volatile memory cells usingthe second plurality of sense amplifiers comprises the second pluralityof sense amplifiers on the control die sensing conditions of the secondplurality of memory cells via the second plurality of bit lines inresponse to the read reference voltage on the selected word line. 20.The method of 18, wherein: the performing the memory operation on thefirst portion of the first block of the non-volatile memory cells usingthe first plurality of sense amplifiers comprises the first plurality ofsense amplifiers on the memory die providing programming conditions onthe first plurality of bit lines while a program voltage is driven onthe selected word line; and the performing the memory operation on thesecond portion of the first block of the non-volatile memory cells usingthe second plurality of sense amplifiers comprises the second pluralityof sense amplifiers on the control die providing programming conditionson the second plurality of bit lines while a program voltage is drivenon the selected word line.